Re: [PATCH] MIPS: KASLR: Fix sync_icache() trapped in loop when synci_step is zero

[Thomas Bogendoerfer <tsbogend@alpha.franken.de>]

On Thu, Dec 03, 2020 at 12:02:10PM +0800, Jiaxun Yang wrote:
> 
> 
> 在 2020/12/2 下午6:39, Thomas Bogendoerfer 写道:
> > On Wed, Dec 02, 2020 at 11:00:05AM +0800, Jinyang He wrote:
> > > Reading synci_step by using rdhwr instruction may return zero if no cache
> > > need be synchronized. On the one hand, to make sure all load operation and
> > > store operation finished we do __sync() for every platform. On the other
> > > hand, some platform need operate synci one time although step is zero.
> > Should this be someting like: Avoid endless loop, if no synci is needed ?
> > 
> > > diff --git a/arch/mips/kernel/relocate.c b/arch/mips/kernel/relocate.c
> > > index 57bdd276..47aeb33 100644
> > > --- a/arch/mips/kernel/relocate.c
> > > +++ b/arch/mips/kernel/relocate.c
> > > @@ -64,7 +64,7 @@ static void __init sync_icache(void *kbase, unsigned long kernel_length)
> > >   			: "r" (kbase));
> > >   		kbase += step;
> > > -	} while (kbase < kend);
> > > +	} while (step && kbase < kend);
> > why not do a
> > 
> > 	if (step == 0)
> > 		return;
> > 
> > before entering the loop ? According to MIPS32PRA no synci is needed,
> > if stepi value is zero.
> > 
> > Thomas.
> > 
> > PS: Does anybody know a reason, why this code doesn't use an old fashioned
> > dache/icache flushing, which might be slower but would work also on
> > legecy cores ?
> 
> I thought that's because legacy flush requires much more cares.

that's true. It shouldn't be that hard, but probably has to wait until
someone needs it.

Thomas.

-- 
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