From: Andre Przywara <andre.przywara@arm.com>
To: Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@siol.net>
Cc: "Icenowy Zheng" <icenowy@aosc.xyz>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Clément Péron" <peron.clem@gmail.com>,
"Shuosheng Huang" <huangshuosheng@allwinnertech.com>,
"Yangtao Li" <tiny.windzz@gmail.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
linux-clk@vger.kernel.org
Subject: [PATCH v2 01/21] clk: sunxi-ng: h6: Fix clock divider range on some clocks
Date: Fri, 11 Dec 2020 01:19:14 +0000 [thread overview]
Message-ID: <20201211011934.6171-2-andre.przywara@arm.com> (raw)
In-Reply-To: <20201211011934.6171-1-andre.przywara@arm.com>
While comparing clocks between the H6 and H616, some of the M factor
ranges were found to be wrong: the manual says they are only covering
two bits [1:0], but our code had "5" in the number-of-bits field.
By writing 0xff into that register in U-Boot and via FEL, it could be
confirmed that bits [4:2] are indeed masked off, so the manual is right.
Change to number of bits in the affected clock's description.
Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index f2497d0a4683..d0565d378ea2 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -237,7 +237,7 @@ static const char * const psi_ahb1_ahb2_parents[] = { "osc24M", "osc32k",
static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
psi_ahb1_ahb2_parents,
0x510,
- 0, 5, /* M */
+ 0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
@@ -246,19 +246,19 @@ static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k",
"psi-ahb1-ahb2",
"pll-periph0" };
static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
- 0, 5, /* M */
+ 0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
- 0, 5, /* M */
+ 0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
- 0, 5, /* M */
+ 0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
--
2.17.5
next prev parent reply other threads:[~2020-12-11 1:21 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-11 1:19 [PATCH v2 00/21] arm64: sunxi: Initial Allwinner H616 SoC support Andre Przywara
2020-12-11 1:19 ` Andre Przywara [this message]
2020-12-11 1:19 ` [PATCH v2 02/21] dt-bindings: pinctrl: Add Allwinner H616 compatible strings Andre Przywara
2020-12-14 9:37 ` Maxime Ripard
2021-01-14 0:45 ` Andre Przywara
2021-01-14 11:57 ` Maxime Ripard
2020-12-11 1:19 ` [PATCH v2 03/21] pinctrl: sunxi: Add support for the Allwinner H616 pin controller Andre Przywara
2020-12-14 9:44 ` Maxime Ripard
2020-12-11 1:19 ` [PATCH v2 04/21] pinctrl: sunxi: Add support for the Allwinner H616-R " Andre Przywara
2020-12-11 1:19 ` [PATCH v2 05/21] dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 Andre Przywara
2020-12-14 22:53 ` Rob Herring
2020-12-11 1:19 ` [PATCH v2 06/21] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU Andre Przywara
2020-12-11 1:19 ` [PATCH v2 07/21] clk: sunxi-ng: Add support for the Allwinner H616 CCU Andre Przywara
2020-12-11 1:19 ` [PATCH v2 08/21] dt-bindings: mmc: sunxi: Add Allwinner A100 and H616 compatibles Andre Przywara
2020-12-14 22:54 ` Rob Herring
2021-01-11 18:06 ` Ulf Hansson
2020-12-11 1:19 ` [PATCH v2 09/21] mmc: sunxi: add support for A100 mmc controller Andre Przywara
2021-01-11 18:06 ` Ulf Hansson
2020-12-11 1:19 ` [PATCH v2 10/21] mfd: axp20x: Allow AXP chips without interrupt lines Andre Przywara
2020-12-11 1:19 ` [PATCH v2 11/21] dt-bindings: sram: sunxi-sram: Add H616 compatible string Andre Przywara
2020-12-14 22:54 ` Rob Herring
2020-12-11 1:19 ` [PATCH v2 12/21] soc: sunxi: sram: Add support for more than one EMAC clock Andre Przywara
2020-12-11 1:19 ` [PATCH v2 13/21] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register Andre Przywara
2020-12-11 1:19 ` [PATCH v2 14/21] phy: sun4i-usb: Rework "pmu_unk1" handling Andre Przywara
2020-12-13 18:24 ` Icenowy Zheng
2020-12-14 1:35 ` André Przywara
2020-12-14 4:45 ` Icenowy Zheng
2020-12-11 1:19 ` [PATCH v2 15/21] phy: sun4i-usb: Add support for the H616 USB PHY Andre Przywara
2020-12-14 9:52 ` Maxime Ripard
2020-12-11 1:19 ` [PATCH v2 16/21] dt-bindings: watchdog: sun4i: Add A100 compatible Andre Przywara
2020-12-13 16:12 ` Guenter Roeck
2020-12-11 1:19 ` [PATCH v2 17/21] dt-bindings: watchdog: sun4i: Add H616 compatible string Andre Przywara
2020-12-14 22:55 ` Rob Herring
2021-01-23 17:29 ` Guenter Roeck
2020-12-11 1:19 ` [PATCH v2 18/21] dt-bindings: allwinner: Add H616 compatible strings Andre Przywara
2020-12-14 22:56 ` Rob Herring
2021-01-05 16:29 ` Wolfram Sang
2020-12-11 1:19 ` [PATCH v2 19/21] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Andre Przywara
2020-12-14 9:58 ` Maxime Ripard
2020-12-14 12:53 ` Andre Przywara
2020-12-14 13:28 ` [linux-sunxi] " Chen-Yu Tsai
2020-12-14 14:14 ` Maxime Ripard
2020-12-14 14:12 ` Maxime Ripard
2020-12-11 1:19 ` [PATCH v2 20/21] dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding Andre Przywara
2020-12-14 22:56 ` Rob Herring
2020-12-11 1:19 ` [PATCH v2 21/21] arm64: dts: allwinner: Add OrangePi Zero 2 .dts Andre Przywara
2020-12-14 9:59 ` Maxime Ripard
2020-12-13 17:47 ` [PATCH v2 00/21] arm64: sunxi: Initial Allwinner H616 SoC support Icenowy Zheng
2020-12-14 1:18 ` André Przywara
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