From: "André Przywara" <andre.przywara@arm.com>
To: Icenowy Zheng <icenowy@aosc.io>,
Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@siol.net>
Cc: "Icenowy Zheng" <icenowy@aosc.xyz>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Rob Herring" <robh@kernel.org>,
"Clément Péron" <peron.clem@gmail.com>,
"Shuosheng Huang" <huangshuosheng@allwinnertech.com>,
"Yangtao Li" <tiny.windzz@gmail.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,
"Kishon Vijay Abraham I" <kishon@ti.com>,
"Vinod Koul" <vkoul@kernel.org>
Subject: Re: [PATCH v2 14/21] phy: sun4i-usb: Rework "pmu_unk1" handling
Date: Mon, 14 Dec 2020 01:35:37 +0000 [thread overview]
Message-ID: <86fd61f1-9bdd-5004-758b-8e21134fadd2@arm.com> (raw)
In-Reply-To: <02cbecddf07dc46f8fb7e0d93b7532e3c239084e.camel@aosc.io>
On 13/12/2020 18:24, Icenowy Zheng wrote:
> 在 2020-12-11星期五的 01:19 +0000，Andre Przywara写道：
>> Newer SoCs (A100, H616) need to clear a different bit in our
>> "unknown"
>> PMU PHY register.
>
> It looks like that the unknown PHY register is PHYCTL register for each
> individual PHY, and the bit that is cleared is
> called SUNXI_HCI_PHY_CTRL_SIDDQ in the BSP (similar to
> the USBC_PHY_CTL_SIDDQ we cleared for main PHYCTL).
Oh, right, somehow I failed to find this in the BSP, I guess I got
confused over that similar symbol. I will put proper names to it.
Thanks!
Andre
>>
>> Generalise the existing code by allowing configs to specify a bitmask
>> of bits to clear.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>> drivers/phy/allwinner/phy-sun4i-usb.c | 28 +++++++++++------------
>> ----
>> 1 file changed, 11 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
>> b/drivers/phy/allwinner/phy-sun4i-usb.c
>> index 651d5e2a25ce..4ba0699e0bb4 100644
>> --- a/drivers/phy/allwinner/phy-sun4i-usb.c
>> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c
>> @@ -115,9 +115,9 @@ struct sun4i_usb_phy_cfg {
>> int hsic_index;
>> enum sun4i_usb_phy_type type;
>> u32 disc_thresh;
>> + u32 pmu_unk1_clrbits;
>> u8 phyctl_offset;
>> bool dedicated_clocks;
>> - bool enable_pmu_unk1;
>> bool phy0_dual_route;
>> int missing_phys;
>> };
>> @@ -288,6 +288,12 @@ static int sun4i_usb_phy_init(struct phy *_phy)
>> return ret;
>> }
>>
>> + if (phy->pmu && data->cfg->pmu_unk1_clrbits) {
>> + val = readl(phy->pmu + REG_PMU_UNK1);
>> + val &= ~data->cfg->pmu_unk1_clrbits;
>> + writel(val, phy->pmu + REG_PMU_UNK1);
>> + }
>> +
>> if (data->cfg->type == sun8i_a83t_phy ||
>> data->cfg->type == sun50i_h6_phy) {
>> if (phy->index == 0) {
>> @@ -297,11 +303,6 @@ static int sun4i_usb_phy_init(struct phy *_phy)
>> writel(val, data->base + data->cfg-
>>> phyctl_offset);
>> }
>> } else {
>> - if (phy->pmu && data->cfg->enable_pmu_unk1) {
>> - val = readl(phy->pmu + REG_PMU_UNK1);
>> - writel(val & ~2, phy->pmu + REG_PMU_UNK1);
>> - }
>> -
>> /* Enable USB 45 Ohm resistor calibration */
>> if (phy->index == 0)
>> sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
>> 0x01, 1);
>> @@ -867,7 +868,6 @@ static const struct sun4i_usb_phy_cfg
>> sun4i_a10_cfg = {
>> .disc_thresh = 3,
>> .phyctl_offset = REG_PHYCTL_A10,
>> .dedicated_clocks = false,
>> - .enable_pmu_unk1 = false,
>> };
>>
>> static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
>> @@ -876,7 +876,6 @@ static const struct sun4i_usb_phy_cfg
>> sun5i_a13_cfg = {
>> .disc_thresh = 2,
>> .phyctl_offset = REG_PHYCTL_A10,
>> .dedicated_clocks = false,
>> - .enable_pmu_unk1 = false,
>> };
>>
>> static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
>> @@ -885,7 +884,6 @@ static const struct sun4i_usb_phy_cfg
>> sun6i_a31_cfg = {
>> .disc_thresh = 3,
>> .phyctl_offset = REG_PHYCTL_A10,
>> .dedicated_clocks = true,
>> - .enable_pmu_unk1 = false,
>> };
>>
>> static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
>> @@ -894,7 +892,6 @@ static const struct sun4i_usb_phy_cfg
>> sun7i_a20_cfg = {
>> .disc_thresh = 2,
>> .phyctl_offset = REG_PHYCTL_A10,
>> .dedicated_clocks = false,
>> - .enable_pmu_unk1 = false,
>> };
>>
>> static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
>> @@ -903,7 +900,6 @@ static const struct sun4i_usb_phy_cfg
>> sun8i_a23_cfg = {
>> .disc_thresh = 3,
>> .phyctl_offset = REG_PHYCTL_A10,
>> .dedicated_clocks = true,
>> - .enable_pmu_unk1 = false,
>> };
>>
>> static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
>> @@ -912,7 +908,6 @@ static const struct sun4i_usb_phy_cfg
>> sun8i_a33_cfg = {
>> .disc_thresh = 3,
>> .phyctl_offset = REG_PHYCTL_A33,
>> .dedicated_clocks = true,
>> - .enable_pmu_unk1 = false,
>> };
>>
>> static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
>> @@ -929,7 +924,7 @@ static const struct sun4i_usb_phy_cfg
>> sun8i_h3_cfg = {
>> .disc_thresh = 3,
>> .phyctl_offset = REG_PHYCTL_A33,
>> .dedicated_clocks = true,
>> - .enable_pmu_unk1 = true,
>> + .pmu_unk1_clrbits = BIT(1),
>> .phy0_dual_route = true,
>> };
>>
>> @@ -939,7 +934,7 @@ static const struct sun4i_usb_phy_cfg
>> sun8i_r40_cfg = {
>> .disc_thresh = 3,
>> .phyctl_offset = REG_PHYCTL_A33,
>> .dedicated_clocks = true,
>> - .enable_pmu_unk1 = true,
>> + .pmu_unk1_clrbits = BIT(1),
>> .phy0_dual_route = true,
>> };
>>
>> @@ -949,7 +944,7 @@ static const struct sun4i_usb_phy_cfg
>> sun8i_v3s_cfg = {
>> .disc_thresh = 3,
>> .phyctl_offset = REG_PHYCTL_A33,
>> .dedicated_clocks = true,
>> - .enable_pmu_unk1 = true,
>> + .pmu_unk1_clrbits = BIT(1),
>> .phy0_dual_route = true,
>> };
>>
>> @@ -959,7 +954,7 @@ static const struct sun4i_usb_phy_cfg
>> sun50i_a64_cfg = {
>> .disc_thresh = 3,
>> .phyctl_offset = REG_PHYCTL_A33,
>> .dedicated_clocks = true,
>> - .enable_pmu_unk1 = true,
>> + .pmu_unk1_clrbits = BIT(1),
>> .phy0_dual_route = true,
>> };
>>
>> @@ -969,7 +964,6 @@ static const struct sun4i_usb_phy_cfg
>> sun50i_h6_cfg = {
>> .disc_thresh = 3,
>> .phyctl_offset = REG_PHYCTL_A33,
>> .dedicated_clocks = true,
>> - .enable_pmu_unk1 = true,
>> .phy0_dual_route = true,
>> .missing_phys = BIT(1) | BIT(2),
>> };
next prev parent reply other threads:[~2020-12-14 1:36 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-11 1:19 [PATCH v2 00/21] arm64: sunxi: Initial Allwinner H616 SoC support Andre Przywara
2020-12-11 1:19 ` [PATCH v2 01/21] clk: sunxi-ng: h6: Fix clock divider range on some clocks Andre Przywara
2020-12-11 1:19 ` [PATCH v2 02/21] dt-bindings: pinctrl: Add Allwinner H616 compatible strings Andre Przywara
2020-12-14 9:37 ` Maxime Ripard
2021-01-14 0:45 ` Andre Przywara
2021-01-14 11:57 ` Maxime Ripard
2020-12-11 1:19 ` [PATCH v2 03/21] pinctrl: sunxi: Add support for the Allwinner H616 pin controller Andre Przywara
2020-12-14 9:44 ` Maxime Ripard
2020-12-11 1:19 ` [PATCH v2 04/21] pinctrl: sunxi: Add support for the Allwinner H616-R " Andre Przywara
2020-12-11 1:19 ` [PATCH v2 05/21] dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 Andre Przywara
2020-12-14 22:53 ` Rob Herring
2020-12-11 1:19 ` [PATCH v2 06/21] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU Andre Przywara
2020-12-11 1:19 ` [PATCH v2 07/21] clk: sunxi-ng: Add support for the Allwinner H616 CCU Andre Przywara
2020-12-11 1:19 ` [PATCH v2 08/21] dt-bindings: mmc: sunxi: Add Allwinner A100 and H616 compatibles Andre Przywara
2020-12-14 22:54 ` Rob Herring
2021-01-11 18:06 ` Ulf Hansson
2020-12-11 1:19 ` [PATCH v2 09/21] mmc: sunxi: add support for A100 mmc controller Andre Przywara
2021-01-11 18:06 ` Ulf Hansson
2020-12-11 1:19 ` [PATCH v2 10/21] mfd: axp20x: Allow AXP chips without interrupt lines Andre Przywara
2020-12-11 1:19 ` [PATCH v2 11/21] dt-bindings: sram: sunxi-sram: Add H616 compatible string Andre Przywara
2020-12-14 22:54 ` Rob Herring
2020-12-11 1:19 ` [PATCH v2 12/21] soc: sunxi: sram: Add support for more than one EMAC clock Andre Przywara
2020-12-11 1:19 ` [PATCH v2 13/21] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register Andre Przywara
2020-12-11 1:19 ` [PATCH v2 14/21] phy: sun4i-usb: Rework "pmu_unk1" handling Andre Przywara
2020-12-13 18:24 ` Icenowy Zheng
2020-12-14 1:35 ` André Przywara [this message]
2020-12-14 4:45 ` Icenowy Zheng
2020-12-11 1:19 ` [PATCH v2 15/21] phy: sun4i-usb: Add support for the H616 USB PHY Andre Przywara
2020-12-14 9:52 ` Maxime Ripard
2020-12-11 1:19 ` [PATCH v2 16/21] dt-bindings: watchdog: sun4i: Add A100 compatible Andre Przywara
2020-12-13 16:12 ` Guenter Roeck
2020-12-11 1:19 ` [PATCH v2 17/21] dt-bindings: watchdog: sun4i: Add H616 compatible string Andre Przywara
2020-12-14 22:55 ` Rob Herring
2021-01-23 17:29 ` Guenter Roeck
2020-12-11 1:19 ` [PATCH v2 18/21] dt-bindings: allwinner: Add H616 compatible strings Andre Przywara
2020-12-14 22:56 ` Rob Herring
2021-01-05 16:29 ` Wolfram Sang
2020-12-11 1:19 ` [PATCH v2 19/21] arm64: dts: allwinner: Add Allwinner H616 .dtsi file Andre Przywara
2020-12-14 9:58 ` Maxime Ripard
2020-12-14 12:53 ` Andre Przywara
2020-12-14 13:28 ` [linux-sunxi] " Chen-Yu Tsai
2020-12-14 14:14 ` Maxime Ripard
2020-12-14 14:12 ` Maxime Ripard
2020-12-11 1:19 ` [PATCH v2 20/21] dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding Andre Przywara
2020-12-14 22:56 ` Rob Herring
2020-12-11 1:19 ` [PATCH v2 21/21] arm64: dts: allwinner: Add OrangePi Zero 2 .dts Andre Przywara
2020-12-14 9:59 ` Maxime Ripard
2020-12-13 17:47 ` [PATCH v2 00/21] arm64: sunxi: Initial Allwinner H616 SoC support Icenowy Zheng
2020-12-14 1:18 ` André Przywara
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=86fd61f1-9bdd-5004-758b-8e21134fadd2@arm.com \
--to=andre.przywara@arm.com \
--cc=huangshuosheng@allwinnertech.com \
--cc=icenowy@aosc.io \
--cc=icenowy@aosc.xyz \
--cc=jernej.skrabec@siol.net \
--cc=kishon@ti.com \
--cc=linus.walleij@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-sunxi@googlegroups.com \
--cc=mripard@kernel.org \
--cc=peron.clem@gmail.com \
--cc=robh@kernel.org \
--cc=tiny.windzz@gmail.com \
--cc=vkoul@kernel.org \
--cc=wens@csie.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).