From: Pratyush Yadav <p.yadav@ti.com>
To: Parshuram Raju Thombare <pthombar@cadence.com>
Cc: "broonie@kernel.org" <broonie@kernel.org>,
"lukas@wunner.de" <lukas@wunner.de>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Jayshri Dajiram Pawar <jpawar@cadence.com>,
Milind Parab <mparab@cadence.com>,
Konrad Kociolek <konrad@cadence.com>,
Tudor Ambarus <tudor.ambarus@microchip.com>,
Vignesh Raghavendra <vigneshr@ti.com>
Subject: Re: [PATCH v3 2/2] spi: cadence: add support for Cadence XSPI controller
Date: Wed, 8 Sep 2021 16:51:15 +0530 [thread overview]
Message-ID: <20210908112113.smnwmayjb3jit3eg@ti.com> (raw)
In-Reply-To: <CY4PR07MB275737A008CBB58C4B108D2FC1D49@CY4PR07MB2757.namprd07.prod.outlook.com>
On 08/09/21 07:27AM, Parshuram Raju Thombare wrote:
> >Depends on SPI_MEM as well.
>
> Ok
>
> >I commented on this last time around as well. This does not look right
> >at all. A SPI MEM based driver should *not* need to know anything about
> >the subsystem driving it. That is the entire point of the API.
> >
> >The controller seems to be able to extract the read and write opcodes
> >from the SFDP on its own since you don't pass in that information to
> >cdns_xspi_nor_read(). It looks like it is tied very heavily to a NOR
> >flash, and I am not sure if it can really be used with a NAND flash, or
> >something else entirely.
> >
> >Which makes me wonder how we should handle controllers like these. I
> >don't think they fit in very well with the SPI MEM model, since they
> >can't execute arbitrary SPI MEM commands very well. At the same time we
> >are trying to get rid of mtd/spi-nor/controllers. Dunno...
> >
> >Mark, Tudor, Vignesh, any ideas?
>
> Ok, then for now I will drop ACMD PIO mode and use only STIG mode.
> In STIG mode driver configures bus width and clock edge mode for
> command, address and data for each operation.
But it would reduce performance by a lot, no? I think we should try to
figure out how we can accomodate controllers like this before resorting
to using the slower modes.
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
next prev parent reply other threads:[~2021-09-08 11:21 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-01 12:35 [PATCH v3 0/2] add support for Cadence's XSPI controller Parshuram Thombare
2021-09-01 12:37 ` [PATCH v3 1/2] spi: cadence: add dt-bindings documentation for Cadence " Parshuram Thombare
2021-09-02 12:03 ` Rob Herring
2021-09-03 8:03 ` Parshuram Raju Thombare
2021-09-03 18:17 ` Pratyush Yadav
2021-09-08 6:52 ` Parshuram Raju Thombare
2021-09-08 11:32 ` Pratyush Yadav
2021-09-08 11:58 ` Parshuram Raju Thombare
2021-09-01 12:37 ` [PATCH v3 2/2] spi: cadence: add support " Parshuram Thombare
2021-09-02 14:39 ` Mark Brown
2021-09-03 8:10 ` Parshuram Raju Thombare
2021-09-03 10:18 ` Mark Brown
2021-09-03 10:47 ` Parshuram Raju Thombare
2021-09-03 11:24 ` Mark Brown
2021-09-03 18:56 ` Pratyush Yadav
2021-09-08 7:27 ` Parshuram Raju Thombare
2021-09-08 11:21 ` Pratyush Yadav [this message]
2021-09-08 11:40 ` Parshuram Raju Thombare
2021-09-08 12:24 ` Mark Brown
2021-09-08 16:22 ` Pratyush Yadav
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