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From: Dmitry Osipenko <digetx@gmail.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
	"Jonathan Hunter" <jonathanh@nvidia.com>,
	"Ulf Hansson" <ulf.hansson@linaro.org>,
	"Viresh Kumar" <vireshk@kernel.org>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Peter De Schrijver" <pdeschrijver@nvidia.com>,
	"Mikko Perttunen" <mperttunen@nvidia.com>,
	"Lee Jones" <lee.jones@linaro.org>,
	"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
	"Nishanth Menon" <nm@ti.com>,
	"Adrian Hunter" <adrian.hunter@intel.com>,
	"Michael Turquette" <mturquette@baylibre.com>
Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-pm@vger.kernel.org, linux-pwm@vger.kernel.org,
	linux-mmc@vger.kernel.org, dri-devel@lists.freedesktop.org,
	linux-clk@vger.kernel.org, David Heidelberg <david@ixit.cz>
Subject: [PATCH v15 27/39] soc/tegra: fuse: Reset hardware
Date: Sun, 14 Nov 2021 22:34:23 +0300	[thread overview]
Message-ID: <20211114193435.7705-28-digetx@gmail.com> (raw)
In-Reply-To: <20211114193435.7705-1-digetx@gmail.com>

The FUSE controller is enabled at a boot time. Reset it in order to put
hardware and clock into clean and disabled state.

Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/soc/tegra/fuse/fuse-tegra.c | 25 +++++++++++++++++++++++++
 drivers/soc/tegra/fuse/fuse.h       |  1 +
 2 files changed, 26 insertions(+)

diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c
index f2151815db58..cc032729a143 100644
--- a/drivers/soc/tegra/fuse/fuse-tegra.c
+++ b/drivers/soc/tegra/fuse/fuse-tegra.c
@@ -14,6 +14,7 @@
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
 #include <linux/sys_soc.h>
 
@@ -243,6 +244,30 @@ static int tegra_fuse_probe(struct platform_device *pdev)
 		goto restore;
 	}
 
+	fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse");
+	if (IS_ERR(fuse->rst)) {
+		err = PTR_ERR(fuse->rst);
+		dev_err(&pdev->dev, "failed to get FUSE reset: %pe\n",
+			fuse->rst);
+		goto restore;
+	}
+
+	/*
+	 * FUSE clock is enabled at a boot time, hence this resume/suspend
+	 * disables the clock besides the h/w resetting.
+	 */
+	err = pm_runtime_resume_and_get(&pdev->dev);
+	if (err)
+		goto restore;
+
+	err = reset_control_reset(fuse->rst);
+	pm_runtime_put(&pdev->dev);
+
+	if (err < 0) {
+		dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err);
+		goto restore;
+	}
+
 	/* release the early I/O memory mapping */
 	iounmap(base);
 
diff --git a/drivers/soc/tegra/fuse/fuse.h b/drivers/soc/tegra/fuse/fuse.h
index de58feba0435..1b719d85bd04 100644
--- a/drivers/soc/tegra/fuse/fuse.h
+++ b/drivers/soc/tegra/fuse/fuse.h
@@ -43,6 +43,7 @@ struct tegra_fuse {
 	void __iomem *base;
 	phys_addr_t phys;
 	struct clk *clk;
+	struct reset_control *rst;
 
 	u32 (*read_early)(struct tegra_fuse *fuse, unsigned int offset);
 	u32 (*read)(struct tegra_fuse *fuse, unsigned int offset);
-- 
2.33.1


  parent reply	other threads:[~2021-11-14 19:46 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-14 19:33 [PATCH v15 00/39] NVIDIA Tegra power management patches for 5.17 Dmitry Osipenko
2021-11-14 19:33 ` [PATCH v15 01/39] soc/tegra: Enable runtime PM during OPP state-syncing Dmitry Osipenko
2021-11-14 19:33 ` [PATCH v15 02/39] soc/tegra: Add devm_tegra_core_dev_init_opp_table_common() Dmitry Osipenko
2021-11-14 19:33 ` [PATCH v15 03/39] soc/tegra: Don't print error message when OPPs not available Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 04/39] dt-bindings: clock: tegra-car: Document new clock sub-nodes Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 05/39] clk: tegra: Support runtime PM and power domain Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 06/39] dt-bindings: host1x: Document OPP and power domain properties Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 07/39] dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 08/39] gpu: host1x: Add initial runtime PM and OPP support Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 09/39] gpu: host1x: Add host1x_channel_stop() Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 10/39] drm/tegra: dc: Support OPP and SoC core voltage scaling Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 11/39] drm/tegra: hdmi: Add OPP support Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 12/39] drm/tegra: gr2d: Support generic power domain and runtime PM Dmitry Osipenko
2021-11-28  5:47   ` Michał Mirosław
2021-11-28 21:50     ` Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 13/39] drm/tegra: gr3d: " Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 14/39] drm/tegra: vic: Stop channel on suspend Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 15/39] drm/tegra: nvdec: " Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 16/39] drm/tegra: submit: Remove pm_runtime_enabled() checks Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 17/39] drm/tegra: submit: Add missing pm_runtime_mark_last_busy() Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 18/39] usb: chipidea: tegra: Add runtime PM and OPP support Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 19/39] bus: tegra-gmi: " Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 20/39] pwm: tegra: " Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 21/39] mmc: sdhci-tegra: " Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 22/39] mtd: rawnand: tegra: " Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 23/39] spi: tegra20-slink: Add " Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 24/39] media: dt: bindings: tegra-vde: Convert to schema Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 25/39] media: dt: bindings: tegra-vde: Document OPP and power domain Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 26/39] media: staging: tegra-vde: Support generic " Dmitry Osipenko
2021-11-14 19:34 ` Dmitry Osipenko [this message]
2021-11-14 19:34 ` [PATCH v15 28/39] soc/tegra: fuse: Use resource-managed helpers Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 29/39] soc/tegra: regulators: Prepare for suspend Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 30/39] soc/tegra: pmc: Rename 3d power domains Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 31/39] soc/tegra: pmc: Rename core power domain Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 32/39] soc/tegra: pmc: Enable core domain support for Tegra20 and Tegra30 Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 33/39] ARM: tegra: Rename CPU and EMC OPP table device-tree nodes Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 34/39] ARM: tegra: Add 500MHz entry to Tegra30 memory OPP table Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 35/39] ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 36/39] ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 37/39] ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 38/39] ARM: tegra: Add Memory Client resets to Tegra30 " Dmitry Osipenko
2021-11-14 19:34 ` [PATCH v15 39/39] ARM: tegra20/30: Disable unused host1x hardware Dmitry Osipenko
2021-11-28  5:40 ` [PATCH v15 00/39] NVIDIA Tegra power management patches for 5.17 Michał Mirosław
2021-11-28 22:03   ` Dmitry Osipenko

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