From: Ansuel Smith <ansuelsmth@gmail.com>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Taniya Das <tdas@codeaurora.org>,
Ansuel Smith <ansuelsmth@gmail.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v5 06/15] clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents
Date: Thu, 24 Feb 2022 17:48:22 +0100 [thread overview]
Message-ID: <20220224164831.21475-7-ansuelsmth@gmail.com> (raw)
In-Reply-To: <20220224164831.21475-1-ansuelsmth@gmail.com>
Use ARRAY_SIZE for num_parents instead of hardcoding the value.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++-----------------
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index f18888454b4f..3a9001830f0c 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -380,7 +380,7 @@ static struct clk_rcg gsbi1_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -431,7 +431,7 @@ static struct clk_rcg gsbi2_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -482,7 +482,7 @@ static struct clk_rcg gsbi4_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -533,7 +533,7 @@ static struct clk_rcg gsbi5_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -584,7 +584,7 @@ static struct clk_rcg gsbi6_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -635,7 +635,7 @@ static struct clk_rcg gsbi7_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -699,7 +699,7 @@ static struct clk_rcg gsbi1_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -750,7 +750,7 @@ static struct clk_rcg gsbi2_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -801,7 +801,7 @@ static struct clk_rcg gsbi4_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -852,7 +852,7 @@ static struct clk_rcg gsbi5_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -903,7 +903,7 @@ static struct clk_rcg gsbi6_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -954,7 +954,7 @@ static struct clk_rcg gsbi7_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1106,7 +1106,7 @@ static struct clk_rcg gp0_src = {
.hw.init = &(struct clk_init_data){
.name = "gp0_src",
.parent_data = gcc_pxo_pll8_cxo,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1157,7 +1157,7 @@ static struct clk_rcg gp1_src = {
.hw.init = &(struct clk_init_data){
.name = "gp1_src",
.parent_data = gcc_pxo_pll8_cxo,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1208,7 +1208,7 @@ static struct clk_rcg gp2_src = {
.hw.init = &(struct clk_init_data){
.name = "gp2_src",
.parent_data = gcc_pxo_pll8_cxo,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1264,7 +1264,7 @@ static struct clk_rcg prng_src = {
.hw.init = &(struct clk_init_data){
.name = "prng_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
},
@@ -1328,7 +1328,7 @@ static struct clk_rcg sdc1_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc1_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1378,7 +1378,7 @@ static struct clk_rcg sdc3_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc3_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1463,7 +1463,7 @@ static struct clk_rcg tsif_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1627,7 +1627,7 @@ static struct clk_rcg pcie_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "pcie_ref_src",
.parent_data = gcc_pxo_pll3,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1721,7 +1721,7 @@ static struct clk_rcg pcie1_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "pcie1_ref_src",
.parent_data = gcc_pxo_pll3,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1815,7 +1815,7 @@ static struct clk_rcg pcie2_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "pcie2_ref_src",
.parent_data = gcc_pxo_pll3,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1914,7 +1914,7 @@ static struct clk_rcg sata_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "sata_ref_src",
.parent_data = gcc_pxo_pll3,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2055,7 +2055,7 @@ static struct clk_rcg usb30_master_clk_src = {
.hw.init = &(struct clk_init_data){
.name = "usb30_master_ref_src",
.parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2129,7 +2129,7 @@ static struct clk_rcg usb30_utmi_clk = {
.hw.init = &(struct clk_init_data){
.name = "usb30_utmi_clk",
.parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2203,7 +2203,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_src",
.parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2269,7 +2269,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_src",
.parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2405,7 +2405,7 @@ static struct clk_dyn_rcg gmac_core1_src = {
.hw.init = &(struct clk_init_data){
.name = "gmac_core1_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
@@ -2477,7 +2477,7 @@ static struct clk_dyn_rcg gmac_core2_src = {
.hw.init = &(struct clk_init_data){
.name = "gmac_core2_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
@@ -2549,7 +2549,7 @@ static struct clk_dyn_rcg gmac_core3_src = {
.hw.init = &(struct clk_init_data){
.name = "gmac_core3_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
@@ -2621,7 +2621,7 @@ static struct clk_dyn_rcg gmac_core4_src = {
.hw.init = &(struct clk_init_data){
.name = "gmac_core4_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
@@ -2681,7 +2681,7 @@ static struct clk_dyn_rcg nss_tcm_src = {
.hw.init = &(struct clk_init_data){
.name = "nss_tcm_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
@@ -2759,7 +2759,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = {
.hw.init = &(struct clk_init_data){
.name = "ubi32_core1_src_clk",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
@@ -2812,7 +2812,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
.hw.init = &(struct clk_init_data){
.name = "ubi32_core2_src_clk",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
--
2.34.1
next prev parent reply other threads:[~2022-02-24 16:49 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-24 16:48 [PATCH v5 00/15] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
2022-02-24 16:48 ` [PATCH v5 01/15] dt-bindings: clock: split qcom,gcc.yaml to common and specific schema Ansuel Smith
2022-02-24 18:43 ` Rob Herring
2022-02-24 22:04 ` Stephen Boyd
2022-03-23 13:55 ` Rob Herring
2022-03-23 19:47 ` Ansuel Smith
2022-03-24 13:16 ` Rob Herring
2022-02-24 16:48 ` [PATCH v5 02/15] dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation Ansuel Smith
2022-02-24 18:46 ` Rob Herring
2022-02-24 18:50 ` Ansuel Smith
2022-02-24 16:48 ` [PATCH v5 03/15] dt-bindings: clock: document qcom,gcc-ipq8064 binding Ansuel Smith
2022-02-24 19:09 ` Rob Herring
2022-02-24 22:07 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 04/15] clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0 Ansuel Smith
2022-02-24 22:07 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 05/15] clk: qcom: gcc-ipq806x: convert parent_names to parent_data Ansuel Smith
2022-02-24 22:09 ` Stephen Boyd
2022-02-24 16:48 ` Ansuel Smith [this message]
2022-02-24 22:09 ` [PATCH v5 06/15] clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 07/15] clk: qcom: gcc-ipq806x: add additional freq nss cores Ansuel Smith
2022-02-24 22:10 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 08/15] clk: qcom: gcc-ipq806x: add unusued flag for critical clock Ansuel Smith
2022-02-24 16:48 ` [PATCH v5 09/15] clk: qcom: clk-rcg: add clk_rcg_floor_ops ops Ansuel Smith
2022-02-24 22:11 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 10/15] clk: qcom: gcc-ipq806x: add additional freq for sdc table Ansuel Smith
2022-02-24 22:11 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 11/15] dt-bindings: clock: add ipq8064 ce5 clk define Ansuel Smith
2022-02-24 19:09 ` Rob Herring
2022-02-24 22:12 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 12/15] clk: qcom: gcc-ipq806x: add CryptoEngine clocks Ansuel Smith
2022-02-24 22:13 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 13/15] dt-bindings: reset: add ipq8064 ce5 resets Ansuel Smith
2022-02-24 19:10 ` Rob Herring
2022-02-24 22:13 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 14/15] clk: qcom: gcc-ipq806x: add CryptoEngine resets Ansuel Smith
2022-02-24 22:13 ` Stephen Boyd
2022-02-24 16:48 ` [PATCH v5 15/15] ARM: dts: qcom: add syscon and cxo/pxo clock to gcc node for ipq8064 Ansuel Smith
2022-02-24 22:14 ` Stephen Boyd
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