[PATCH] x86/mce: fix failed to reenable cmci when swiching to interrupt mode

* [PATCH] x86/mce: fix failed to reenable cmci when swiching to interrupt mode
@ 2015-08-11 10:09 Xie XiuQi
  2015-08-11 14:46 ` Borislav Petkov
  0 siblings, 1 reply; 5+ messages in thread
From: Xie XiuQi @ 2015-08-11 10:09 UTC (permalink / raw)
  To: tony.luck, bp, tglx, mingo, hpa
  Cc: x86, linux-edac, linux-kernel, zhangliguang

Zhang Liguang report a bug as bellow:
1) system detected cmci storm on current cpu
2) disable cmci interrupt on banks ownd by current cpu, then swiching to poll mode
3) a few minites later, system swiching to interrupt mode on current cpu
4) we expect system to reenable cmci interrupt on banks ownd by current cpu
   mce_intel_adjust_timer
   |-> cmci_reenable
       |-> cmci_discover     # but, ownd banks is ignore here

> static void cmci_discover(int banks)
>	...
>	for (i = 0; i < banks; i++) {
>		...
>		if (test_bit(i, owned))	# ownd banks is ignore here
>			continue;

In this patch, we add a func cmci_storm_enable_banks(), just to enable banks
which ownd by current cpu without clean the ownd flags. We call this func
instead of cmci_reenble() when swiching to interrupt mode.

Reported-by: Zhang Liguang <zhangliguang@huawei.com>
Cc: stable@vger.kernel.org  # v4.1+
Signed-off-by: Xie XiuQi <xiexiuqi@huawei.com>
---
 arch/x86/kernel/cpu/mcheck/mce_intel.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index 844f56c..d4e98c7 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -146,6 +146,22 @@ void mce_intel_hcpu_update(unsigned long cpu)
 	per_cpu(cmci_storm_state, cpu) = CMCI_STORM_NONE;
 }
 
+static void cmci_storm_enable_banks(void)
+{
+	unsigned long flags, *owned;
+	int bank;
+	u64 val;
+
+	raw_spin_lock_irqsave(&cmci_discover_lock, flags);
+	owned = this_cpu_ptr(mce_banks_owned);
+	for_each_set_bit(bank, owned, MAX_NR_BANKS) {
+		rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
+		val |= MCI_CTL2_CMCI_EN;
+		wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
+	}
+	raw_spin_unlock_irqrestore(&cmci_discover_lock, flags);
+}
+
 unsigned long cmci_intel_adjust_timer(unsigned long interval)
 {
 	if ((this_cpu_read(cmci_backoff_cnt) > 0) &&
@@ -175,7 +191,7 @@ unsigned long cmci_intel_adjust_timer(unsigned long interval)
 		 */
 		if (!atomic_read(&cmci_storm_on_cpus)) {
 			__this_cpu_write(cmci_storm_state, CMCI_STORM_NONE);
-			cmci_reenable();
+			cmci_storm_enable_banks();
 			cmci_recheck();
 		}
 		return CMCI_POLL_INTERVAL;
-- 
2.0.0


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