* [PATCH v2] ARM64: Add new Xilinx ZynqMP SoC
@ 2015-03-05 13:53 Michal Simek
2015-03-05 14:03 ` Thomas Petazzoni
2015-03-05 14:05 ` Marc Zyngier
0 siblings, 2 replies; 5+ messages in thread
From: Michal Simek @ 2015-03-05 13:53 UTC (permalink / raw)
To: linux-arm-kernel, Mark Rutland, Rob Herring
Cc: Zach Pfeffer, Catalin Marinas, Will Deacon, Rob Herring,
Pawel Moll, Ian Campbell, Kumar Gala, Sören Brinkmann,
Robert Richter, Mark Brown, Eddie Huang, linux-kernel,
devicetree
Initial version of device tree for Xilinx ZynqMP SoC.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
---
Changes in v2:
- move timer out of amba_apu bus because it is not on bus
Reported by Mark
- FIC GICC and GICV addresses - Reported by Rob
- Fix copyright
- Enable cadence IP in defconfig
- Add support for macb multiqueue
arch/arm64/Kconfig | 5 +
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/xilinx/Makefile | 5 +
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 47 +++++
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 303 ++++++++++++++++++++++++++++
arch/arm64/configs/defconfig | 3 +
6 files changed, 364 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/Makefile
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp.dtsi
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 1b8e97331ffb..9f805cf2e0b0 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -228,6 +228,11 @@ config ARCH_XGENE
help
This enables support for AppliedMicro X-Gene SOC Family
+config ARCH_ZYNQMP
+ bool "Xilinx ZynqMP Family"
+ help
+ This enables support for Xilinx ZynqMP Family
+
endmenu
menu "Bus support"
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index e0350caf049e..ff088ec6ca5f 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -5,5 +5,6 @@ dts-dirs += cavium
dts-dirs += exynos
dts-dirs += freescale
dts-dirs += mediatek
+dts-dirs += xilinx
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
new file mode 100644
index 000000000000..ae16427f6a4a
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -0,0 +1,5 @@
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files := *.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
new file mode 100644
index 000000000000..0a3f40ecd06d
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
@@ -0,0 +1,47 @@
+/*
+ * dts file for Xilinx ZynqMP ep108 development board
+ *
+ * (C) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/dts-v1/;
+
+/include/ "zynqmp.dtsi"
+
+/ {
+ model = "ZynqMP EP108";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x40000000>;
+ };
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0{
+ reg = <0>;
+ max-speed = <100>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
new file mode 100644
index 000000000000..c5f140a34856
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -0,0 +1,303 @@
+/*
+ * dts file for Xilinx ZynqMP
+ *
+ * (C) Copyright 2014 - 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+/ {
+ compatible = "xlnx,zynqmp";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0>;
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x1>;
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x2>;
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x3>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 143 4>,
+ <0 144 4>,
+ <0 145 4>,
+ <0 146 4>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <1 13 0xff01>,
+ <1 14 0xff01>,
+ <1 11 0xff01>,
+ <1 10 0xff01>;
+ };
+
+ amba_apu {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ gic: interrupt-controller@f9010000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ reg = <0x0 0xf9010000 0x10000>,
+ <0x0 0xf902f000 0x2000>,
+ <0x0 0xf9040000 0x20000>,
+ <0x0 0xf906f000 0x2000>;
+ interrupt-controller;
+ };
+ };
+
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ misc_clk: misc_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ ttc0: timer@ff110000 {
+ compatible = "cdns,ttc";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
+ reg = <0x0 0xff110000 0x1000>;
+ clocks = <&misc_clk>;
+ timer-width = <32>;
+ };
+
+ ttc1: timer@ff120000 {
+ compatible = "cdns,ttc";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
+ reg = <0x0 0xff120000 0x1000>;
+ clocks = <&misc_clk>;
+ timer-width = <32>;
+ };
+
+ ttc2: timer@ff130000 {
+ compatible = "cdns,ttc";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
+ reg = <0x0 0xff130000 0x1000>;
+ clocks = <&misc_clk>;
+ timer-width = <32>;
+ };
+
+ ttc3: timer@ff140000 {
+ compatible = "cdns,ttc";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
+ reg = <0x0 0xff140000 0x1000>;
+ clocks = <&misc_clk>;
+ timer-width = <32>;
+ };
+
+ uart0: serial@ff000000 {
+ compatible = "cdns,uart-r1p8";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 21 4>;
+ reg = <0x0 0xff000000 0x1000>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&misc_clk &misc_clk>;
+ };
+
+ uart1: serial@ff010000 {
+ compatible = "cdns,uart-r1p8";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 22 4>;
+ reg = <0x0 0xff010000 0x1000>;
+ clock-names = "uart_clk", "pclk";
+ clocks = <&misc_clk &misc_clk>;
+ };
+
+ gpio: gpio@ff0a0000 {
+ compatible = "xlnx,zynq-gpio-1.0";
+ status = "disabled";
+ #gpio-cells = <0x2>;
+ clocks = <&misc_clk>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 16 4>;
+ reg = <0x0 0xff0a0000 0x1000>;
+ };
+
+ gem0: ethernet@ff0b0000 {
+ compatible = "cdns,gem";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 57 4>, <0 57 4>;
+ reg = <0x0 0xff0b0000 0x1000>;
+ clock-names = "pclk", "hclk", "tx_clk";
+ clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gem1: ethernet@ff0c0000 {
+ compatible = "cdns,gem";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 59 4>, <0 59 4>;
+ reg = <0x0 0xff0c0000 0x1000>;
+ clock-names = "pclk", "hclk", "tx_clk";
+ clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gem2: ethernet@ff0d0000 {
+ compatible = "cdns,gem";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 61 4>, <0 61 4>;
+ reg = <0x0 0xff0d0000 0x1000>;
+ clock-names = "pclk", "hclk", "tx_clk";
+ clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ gem3: ethernet@ff0e0000 {
+ compatible = "cdns,gem";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 63 4>, <0 63 4>;
+ reg = <0x0 0xff0e0000 0x1000>;
+ clock-names = "pclk", "hclk", "tx_clk";
+ clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi0: spi@ff040000 {
+ compatible = "cdns,spi-r1p6";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 19 4>;
+ reg = <0x0 0xff040000 0x1000>;
+ clock-names = "ref_clk", "pclk";
+ clocks = <&misc_clk &misc_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@ff050000 {
+ compatible = "cdns,spi-r1p6";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 20 4>;
+ reg = <0x0 0xff050000 0x1000>;
+ clock-names = "ref_clk", "pclk";
+ clocks = <&misc_clk &misc_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c_clk: i2c_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <111111111>;
+ };
+
+ i2c0: i2c@ff020000 {
+ compatible = "cdns,i2c-r1p10";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 17 4>;
+ reg = <0x0 0xff020000 0x1000>;
+ clocks = <&i2c_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1: i2c@ff030000 {
+ compatible = "cdns,i2c-r1p10";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 18 4>;
+ reg = <0x0 0xff030000 0x1000>;
+ clocks = <&i2c_clk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sdhci0: sdhci@ff160000 {
+ compatible = "arasan,sdhci-8.9a";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 48 4>;
+ reg = <0x0 0xff160000 0x1000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&misc_clk>, <&misc_clk>;
+ };
+
+ sdhci1: sdhci@ff170000 {
+ compatible = "arasan,sdhci-8.9a";
+ status = "disabled";
+ interrupt-parent = <&gic>;
+ interrupts = <0 49 4>;
+ reg = <0x0 0xff170000 0x1000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&misc_clk>, <&misc_clk>;
+ };
+
+ watchdog0: watchdog@fd4d0000 {
+ compatible = "cdns,wdt-r1p2";
+ status = "disabled";
+ clocks= <&misc_clk>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 52 1>;
+ reg = <0x0 0xfd4d0000 0x1000>;
+ timeout-sec = <10>;
+ };
+ };
+};
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index be1f12a5a5f0..c34bfa002303 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -36,6 +36,7 @@ CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_THUNDER=y
CONFIG_ARCH_VEXPRESS=y
CONFIG_ARCH_XGENE=y
+CONFIG_ARCH_ZYNQMP=y
CONFIG_PCI=y
CONFIG_PCI_MSI=y
CONFIG_PCI_XGENE=y
@@ -94,6 +95,8 @@ CONFIG_SERIAL_8250_MT6577=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
CONFIG_VIRTIO_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_SPI=y
--
1.8.2.3
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2] ARM64: Add new Xilinx ZynqMP SoC
2015-03-05 13:53 [PATCH v2] ARM64: Add new Xilinx ZynqMP SoC Michal Simek
@ 2015-03-05 14:03 ` Thomas Petazzoni
2015-03-05 14:08 ` Michal Simek
2015-03-05 14:05 ` Marc Zyngier
1 sibling, 1 reply; 5+ messages in thread
From: Thomas Petazzoni @ 2015-03-05 14:03 UTC (permalink / raw)
To: Michal Simek
Cc: linux-arm-kernel, Mark Rutland, Rob Herring, devicetree,
Zach Pfeffer, Pawel Moll, Ian Campbell, Catalin Marinas,
Mark Brown, Will Deacon, linux-kernel, Robert Richter,
Rob Herring, Kumar Gala, Eddie Huang, Sören Brinkmann
Dear Michal Simek,
On Thu, 5 Mar 2015 14:53:34 +0100, Michal Simek wrote:
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <0 143 4>,
> + <0 144 4>,
> + <0 145 4>,
> + <0 146 4>;
Any reason not to use
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
in order to write the more descriptive:
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
And ditto for all other interrupts properties?
Thanks,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] ARM64: Add new Xilinx ZynqMP SoC
2015-03-05 13:53 [PATCH v2] ARM64: Add new Xilinx ZynqMP SoC Michal Simek
2015-03-05 14:03 ` Thomas Petazzoni
@ 2015-03-05 14:05 ` Marc Zyngier
2015-03-05 14:27 ` Michal Simek
1 sibling, 1 reply; 5+ messages in thread
From: Marc Zyngier @ 2015-03-05 14:05 UTC (permalink / raw)
To: Michal Simek, linux-arm-kernel, Mark Rutland, Rob Herring
Cc: devicetree, Zach Pfeffer, Pawel Moll, Ian Campbell,
Catalin Marinas, Mark Brown, Will Deacon, linux-kernel,
Robert Richter, Rob Herring, Kumar Gala, Eddie Huang,
Sören Brinkmann
Hi Michal,
On 05/03/15 13:53, Michal Simek wrote:
> Initial version of device tree for Xilinx ZynqMP SoC.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
> ---
>
> Changes in v2:
> - move timer out of amba_apu bus because it is not on bus
> Reported by Mark
> - FIC GICC and GICV addresses - Reported by Rob
> - Fix copyright
> - Enable cadence IP in defconfig
> - Add support for macb multiqueue
>
> arch/arm64/Kconfig | 5 +
> arch/arm64/boot/dts/Makefile | 1 +
> arch/arm64/boot/dts/xilinx/Makefile | 5 +
> arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 47 +++++
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 303 ++++++++++++++++++++++++++++
> arch/arm64/configs/defconfig | 3 +
> 6 files changed, 364 insertions(+)
> create mode 100644 arch/arm64/boot/dts/xilinx/Makefile
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp.dtsi
[...]
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
> new file mode 100644
> index 000000000000..0a3f40ecd06d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
[...]
> + gic: interrupt-controller@f9010000 {
> + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + reg = <0x0 0xf9010000 0x10000>,
> + <0x0 0xf902f000 0x2000>,
> + <0x0 0xf9040000 0x20000>,
> + <0x0 0xf906f000 0x2000>;
> + interrupt-controller;
Please add the missing GIC maintenance interrupt.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] ARM64: Add new Xilinx ZynqMP SoC
2015-03-05 14:03 ` Thomas Petazzoni
@ 2015-03-05 14:08 ` Michal Simek
0 siblings, 0 replies; 5+ messages in thread
From: Michal Simek @ 2015-03-05 14:08 UTC (permalink / raw)
To: Thomas Petazzoni, Michal Simek
Cc: linux-arm-kernel, Mark Rutland, Rob Herring, devicetree,
Zach Pfeffer, Pawel Moll, Ian Campbell, Catalin Marinas,
Mark Brown, Will Deacon, linux-kernel, Robert Richter,
Rob Herring, Kumar Gala, Eddie Huang, Sören Brinkmann
[-- Attachment #1: Type: text/plain, Size: 1178 bytes --]
Hi Thomas,
On 03/05/2015 03:03 PM, Thomas Petazzoni wrote:
> Dear Michal Simek,
>
> On Thu, 5 Mar 2015 14:53:34 +0100, Michal Simek wrote:
>
>> + pmu {
>> + compatible = "arm,armv8-pmuv3";
>> + interrupts = <0 143 4>,
>> + <0 144 4>,
>> + <0 145 4>,
>> + <0 146 4>;
>
> Any reason not to use
>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
>
> in order to write the more descriptive:
>
> interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
>
> And ditto for all other interrupts properties?
I tend to not to use them because it is just hassle when I want
to move DTSes to different project.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] ARM64: Add new Xilinx ZynqMP SoC
2015-03-05 14:05 ` Marc Zyngier
@ 2015-03-05 14:27 ` Michal Simek
0 siblings, 0 replies; 5+ messages in thread
From: Michal Simek @ 2015-03-05 14:27 UTC (permalink / raw)
To: Marc Zyngier, Michal Simek, linux-arm-kernel, Mark Rutland, Rob Herring
Cc: devicetree, Zach Pfeffer, Pawel Moll, Ian Campbell,
Catalin Marinas, Mark Brown, Will Deacon, linux-kernel,
Robert Richter, Rob Herring, Kumar Gala, Eddie Huang,
Sören Brinkmann
[-- Attachment #1: Type: text/plain, Size: 2203 bytes --]
Hi Marc,
On 03/05/2015 03:05 PM, Marc Zyngier wrote:
> Hi Michal,
>
> On 05/03/15 13:53, Michal Simek wrote:
>> Initial version of device tree for Xilinx ZynqMP SoC.
>>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
>> ---
>>
>> Changes in v2:
>> - move timer out of amba_apu bus because it is not on bus
>> Reported by Mark
>> - FIC GICC and GICV addresses - Reported by Rob
>> - Fix copyright
>> - Enable cadence IP in defconfig
>> - Add support for macb multiqueue
>>
>> arch/arm64/Kconfig | 5 +
>> arch/arm64/boot/dts/Makefile | 1 +
>> arch/arm64/boot/dts/xilinx/Makefile | 5 +
>> arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 47 +++++
>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 303 ++++++++++++++++++++++++++++
>> arch/arm64/configs/defconfig | 3 +
>> 6 files changed, 364 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/xilinx/Makefile
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>
> [...]
>
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
>> new file mode 100644
>> index 000000000000..0a3f40ecd06d
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
>
> [...]
>
>> + gic: interrupt-controller@f9010000 {
>> + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>> + #interrupt-cells = <3>;
>> + reg = <0x0 0xf9010000 0x10000>,
>> + <0x0 0xf902f000 0x2000>,
>> + <0x0 0xf9040000 0x20000>,
>> + <0x0 0xf906f000 0x2000>;
>> + interrupt-controller;
>
> Please add the missing GIC maintenance interrupt.
Ok. Will add interrupts = <1 9 0xf04>;
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2015-03-05 14:27 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-03-05 13:53 [PATCH v2] ARM64: Add new Xilinx ZynqMP SoC Michal Simek
2015-03-05 14:03 ` Thomas Petazzoni
2015-03-05 14:08 ` Michal Simek
2015-03-05 14:05 ` Marc Zyngier
2015-03-05 14:27 ` Michal Simek
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