From: "Singh, Balbir" <sblbir@amazon.com>
To: "tglx@linutronix.de" <tglx@linutronix.de>,
"mingo@redhat.com" <mingo@redhat.com>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"peterz@infradead.org" <peterz@infradead.org>,
"keescook@chromium.org" <keescook@chromium.org>,
"torvalds@linux-foundation.org" <torvalds@linux-foundation.org>,
"jpoimboe@redhat.com" <jpoimboe@redhat.com>,
"x86@kernel.org" <x86@kernel.org>,
"tony.luck@intel.com" <tony.luck@intel.com>,
"dave.hansen@intel.com" <dave.hansen@intel.com>,
"thomas.lendacky@amd.com" <thomas.lendacky@amd.com>,
"benh@kernel.crashing.org" <benh@kernel.crashing.org>
Subject: Re: [PATCH v3 1/5] x86/mm: change l1d flush runtime prctl behaviour
Date: Fri, 4 Dec 2020 22:44:31 +0000 [thread overview]
Message-ID: <648c2e023a6be09e331eece1a741b573c3fab98a.camel@amazon.com> (raw)
In-Reply-To: <87r1o59t5f.fsf@nanos.tec.linutronix.de>
On Fri, 2020-12-04 at 22:07 +0100, Thomas Gleixner wrote:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you can confirm the sender and know the content is safe.
>
>
>
> On Fri, Nov 27 2020 at 17:59, Balbir Singh wrote:
>
> > Detection of task affinities at API opt-in time is not the best
> > approach, the approach is to kill the task if it runs on a
> > SMT enable core. This is better than not flushing the L1D cache
> > when the task switches from a non-SMT core to an SMT enabled core.
> >
> > Signed-off-by: Balbir Singh <sblbir@amazon.com>
> > ---
> > arch/x86/include/asm/processor.h | 2 ++
> > arch/x86/kernel/smpboot.c | 11 ++++++++++-
> > 2 files changed, 12 insertions(+), 1 deletion(-)
>
> Subject, changelog match but patch content not so much :)
>
The changelog jumped between 1/3 of my fixup and 1/5 of my
new post :)
The correct changelog is below, which I shall fix
x86/smp: Add a per-cpu view of SMT state
A new field smt_active in cpuinfo_x86 identifies if the current core/cpu
is in SMT mode or not. This can be very helpful if the system has some
of its cores with threads offlined and can be used for cases where
action is taken based on the state of SMT. The follow up patches use
this feature.
Suggested-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Balbir Singh <sblbir@amazon.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20200729001103.6450-2-sblbir@amazon.com
---
next prev parent reply other threads:[~2020-12-04 22:45 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-27 6:59 [PATCH v3 0/5] Next revision of the L1D flush patches Balbir Singh
2020-11-27 6:59 ` [PATCH v3 1/5] x86/mm: change l1d flush runtime prctl behaviour Balbir Singh
2020-12-04 21:07 ` Thomas Gleixner
2020-12-04 22:44 ` Singh, Balbir [this message]
2020-11-27 6:59 ` [PATCH v3 2/5] x86/mm: Refactor cond_ibpb() to support other use cases Balbir Singh
2020-11-27 6:59 ` [PATCH v3 3/5] x86/mm: Optionally flush L1D on context switch Balbir Singh
2020-12-04 21:21 ` Thomas Gleixner
2020-12-04 22:41 ` Singh, Balbir
2020-11-27 6:59 ` [PATCH v3 4/5] prctl: Hook L1D flushing in via prctl Balbir Singh
2020-12-04 22:19 ` Thomas Gleixner
2020-12-05 2:56 ` Balbir Singh
2020-11-27 6:59 ` [PATCH v3 5/5] Documentation: Add L1D flushing Documentation Balbir Singh
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