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From: Paolo Bonzini <pbonzini@redhat.com>
To: Anup Patel <anup@brainfault.org>
Cc: Anup Patel <Anup.Patel@wdc.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Radim K <rkrcmar@redhat.com>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Atish Patra <Atish.Patra@wdc.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Damien Le Moal <Damien.LeMoal@wdc.com>,
	Christoph Hellwig <hch@infradead.org>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [RFC PATCH 05/16] RISC-V: KVM: Implement VCPU interrupts and requests handling
Date: Tue, 30 Jul 2019 15:18:56 +0200	[thread overview]
Message-ID: <828f01a9-2f11-34b6-7753-dc8fa7aa0d18@redhat.com> (raw)
In-Reply-To: <CAAhSdy3b-o6y1fsYi1iQcCN=9ZuC98TLCqjHCYAzOCx+N+_89w@mail.gmail.com>

On 30/07/19 14:45, Anup Patel wrote:
> Here's some text from RISC-V spec regarding SIP CSR:
> "software interrupt-pending (SSIP) bit in the sip register. A pending
> supervisor-level software interrupt can be cleared by writing 0 to the SSIP bit
> in sip. Supervisor-level software interrupts are disabled when the SSIE bit in
> the sie register is clear."
> 
> Without RISC-V hypervisor extension, the SIP is essentially a restricted
> view of MIP CSR. Also as-per above, S-mode SW can only write 0 to SSIP
> bit in SIP CSR whereas it can only be set by M-mode SW or some HW
> mechanism (such as S-mode CLINT).

But that's not what the spec says.  It just says (just before the
sentence you quoted):

   A supervisor-level software interrupt is triggered on the current
   hart by writing 1 to its supervisor software interrupt-pending (SSIP)
   bit in the sip register.

and it's not written anywhere that S-mode SW cannot write 1.  In fact
that text is even under sip, not under mip, so IMO there's no doubt that
S-mode SW _can_ write 1, and the hypervisor must operate accordingly.

In fact I'm sure that if Windows were ever ported to RISC-V, it would be
very happy to use that feature.  On x86, Intel even accelerated it
specifically for Microsoft. :)

Paolo

  reply	other threads:[~2019-07-30 13:19 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-29 11:56 [RFC PATCH 00/16] KVM RISC-V Support Anup Patel
2019-07-29 11:56 ` [RFC PATCH 01/16] KVM: RISC-V: Add KVM_REG_RISCV for ONE_REG interface Anup Patel
2019-07-29 11:56 ` [RFC PATCH 02/16] RISC-V: Add hypervisor extension related CSR defines Anup Patel
2019-07-29 11:56 ` [RFC PATCH 03/16] RISC-V: Add initial skeletal KVM support Anup Patel
2019-07-30  9:23   ` Paolo Bonzini
2019-07-30 11:04     ` Anup Patel
2019-07-30  9:25   ` Paolo Bonzini
2019-07-30 11:03     ` Anup Patel
2019-07-29 11:56 ` [RFC PATCH 04/16] RISC-V: KVM: Implement VCPU create, init and destroy functions Anup Patel
2019-07-30  8:48   ` Paolo Bonzini
2019-07-30 10:16     ` Paolo Bonzini
2019-07-30 11:45       ` Anup Patel
2019-07-30 11:47         ` Paolo Bonzini
2019-07-29 11:56 ` [RFC PATCH 05/16] RISC-V: KVM: Implement VCPU interrupts and requests handling Anup Patel
2019-07-30 11:17   ` Paolo Bonzini
2019-07-30 12:00     ` Anup Patel
2019-07-30 12:12       ` Paolo Bonzini
2019-07-30 12:45         ` Anup Patel
2019-07-30 13:18           ` Paolo Bonzini [this message]
2019-07-30 13:35             ` Anup Patel
2019-07-30 14:08               ` Paolo Bonzini
2019-08-02  3:59                 ` Anup Patel
2019-07-29 11:56 ` [RFC PATCH 06/16] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls Anup Patel
2019-07-30  8:43   ` Paolo Bonzini
2019-07-30  9:35     ` Paolo Bonzini
2019-07-30 12:08       ` Anup Patel
2019-07-30 12:10         ` Paolo Bonzini
2019-07-30 12:16           ` Anup Patel
2019-07-29 11:57 ` [RFC PATCH 07/16] RISC-V: KVM: Implement VCPU world-switch Anup Patel
2019-07-30  9:34   ` Paolo Bonzini
2019-07-30 12:51     ` Anup Patel
2019-07-29 11:57 ` [RFC PATCH 08/16] RISC-V: KVM: Handle MMIO exits for VCPU Anup Patel
2019-07-30 11:20   ` Paolo Bonzini
2019-07-31  7:23     ` Anup Patel
2019-07-29 11:57 ` [RFC PATCH 09/16] RISC-V: KVM: Handle WFI " Anup Patel
2019-07-29 11:57 ` [RFC PATCH 10/16] RISC-V: KVM: Implement VMID allocator Anup Patel
2019-07-30  8:59   ` Paolo Bonzini
2019-07-29 11:57 ` [RFC PATCH 11/16] RISC-V: KVM: Implement stage2 page table programming Anup Patel
2019-07-30  9:00   ` Paolo Bonzini
2019-07-30 12:14     ` Anup Patel
2019-07-29 11:57 ` [RFC PATCH 12/16] RISC-V: KVM: Implement MMU notifiers Anup Patel
2019-07-29 11:57 ` [RFC PATCH 13/16] RISC-V: KVM: Add timer functionality Anup Patel
2019-07-29 14:40   ` Andreas Schwab
2019-07-29 18:02     ` Atish Patra
2019-07-30  6:51       ` Andreas Schwab
2019-07-30  7:00         ` Atish Patra
2019-07-30 11:26   ` Paolo Bonzini
2019-07-31  1:55     ` Atish Patra
2019-07-31  6:58       ` Paolo Bonzini
2019-07-31  7:18         ` Anup Patel
2019-07-29 11:57 ` [RFC PATCH 14/16] RISC-V: KVM: FP lazy save/restore Anup Patel
2019-07-29 11:57 ` [RFC PATCH 15/16] RISC-V: KVM: Add SBI v0.1 support Anup Patel
2019-07-29 19:40   ` Paolo Bonzini
2019-07-29 19:51     ` Atish Patra
2019-07-29 20:08       ` Paolo Bonzini
2019-07-29 21:08         ` Atish Patra
2019-07-30  9:26   ` Paolo Bonzini
2019-07-29 11:58 ` [RFC PATCH 16/16] RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig Anup Patel
2019-07-29 21:47 ` [RFC PATCH 00/16] KVM RISC-V Support Paolo Bonzini
2019-07-30  5:26   ` Anup Patel
2019-07-30 11:33     ` Paolo Bonzini
2019-07-30 13:50       ` Anup Patel
2019-07-30 14:02         ` Paolo Bonzini
2019-07-30  6:53 ` Andreas Schwab
2019-07-30  7:25   ` Anup Patel
2019-07-30  7:42     ` Andreas Schwab
2019-07-30  7:36   ` Anup Patel

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