* [PATCH v5 1/2] arm64: dts: qcom: sc7280: Add gpu support
@ 2021-08-11 14:23 Akhil P Oommen
2021-08-11 14:23 ` [PATCH v5 2/2] arm64: dts: qcom: sc7280: Add gpu thermal zone cooling support Akhil P Oommen
2021-08-11 17:51 ` [PATCH v5 1/2] arm64: dts: qcom: sc7280: Add gpu support Stephen Boyd
0 siblings, 2 replies; 3+ messages in thread
From: Akhil P Oommen @ 2021-08-11 14:23 UTC (permalink / raw)
To: freedreno, dri-devel,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm,
Stephen Boyd, Bjorn Andersson, Rob Herring,
Manaf Meethalavalappu Pallikunhi
Cc: Jordan Crouse, Matthias Kaehlcke, Jonathan Marek,
Douglas Anderson, Rob Clark, Andy Gross, linux-kernel
Add the necessary dt nodes for gpu support in sc7280.
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
---
Changes in v5:
- Added Stephen's reviewed-by tag to patch-2
Changes in v4:
- Removed the dependency on gpucc bindings (Stephen)
- Reordered GPU's opp table
Changes in v3:
- Re-ordered the nodes based on address (Stephen)
- Added the patch for gpu cooling to the stack.
Changes in v2:
- formatting update and removed a duplicate header (Stephen)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 115 +++++++++++++++++++++++++++++++++++
1 file changed, 115 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 029723a..b9006d8 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -592,6 +592,85 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ gpu@3d00000 {
+ compatible = "qcom,adreno-635.0", "qcom,adreno";
+ #stream-id-cells = <16>;
+ reg = <0 0x03d00000 0 0x40000>,
+ <0 0x03d9e000 0 0x1000>,
+ <0 0x03d61000 0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&adreno_smmu 0 0x401>;
+ operating-points-v2 = <&gpu_opp_table>;
+ qcom,gmu = <&gmu>;
+ interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "gfx-mem";
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-315000000 {
+ opp-hz = /bits/ 64 <315000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ opp-peak-kBps = <1804000>;
+ };
+
+ opp-450000000 {
+ opp-hz = /bits/ 64 <450000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ opp-peak-kBps = <4068000>;
+ };
+
+ opp-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <6832000>;
+ };
+ };
+ };
+
+ gmu: gmu@3d69000 {
+ compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
+ reg = <0 0x03d6a000 0 0x34000>,
+ <0 0x3de0000 0 0x10000>,
+ <0 0x0b290000 0 0x10000>;
+ reg-names = "gmu", "rscc", "gmu_pdc";
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+ clocks = <&gpucc 5>,
+ <&gpucc 8>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc 2>,
+ <&gpucc 15>,
+ <&gpucc 11>;
+ clock-names = "gmu",
+ "cxo",
+ "axi",
+ "memnoc",
+ "ahb",
+ "hub",
+ "smmu_vote";
+ power-domains = <&gpucc 0>,
+ <&gpucc 1>;
+ power-domain-names = "cx",
+ "gx";
+ iommus = <&adreno_smmu 5 0x400>;
+ operating-points-v2 = <&gmu_opp_table>;
+
+ gmu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+ };
+ };
+
gpucc: clock-controller@3d90000 {
compatible = "qcom,sc7280-gpucc";
reg = <0 0x03d90000 0 0x9000>;
@@ -606,6 +685,42 @@
#power-domain-cells = <1>;
};
+ adreno_smmu: iommu@3da0000 {
+ compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
+ reg = <0 0x03da0000 0 0x20000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc 2>,
+ <&gpucc 11>,
+ <&gpucc 5>,
+ <&gpucc 15>,
+ <&gpucc 13>;
+ clock-names = "gcc_gpu_memnoc_gfx_clk",
+ "gcc_gpu_snoc_dvm_gfx_clk",
+ "gpu_cc_ahb_clk",
+ "gpu_cc_hlos1_vote_gpu_smmu_clk",
+ "gpu_cc_cx_gmu_clk",
+ "gpu_cc_hub_cx_int_clk",
+ "gpu_cc_hub_aon_clk";
+
+ power-domains = <&gpucc 0>;
+ };
+
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH v5 2/2] arm64: dts: qcom: sc7280: Add gpu thermal zone cooling support
2021-08-11 14:23 [PATCH v5 1/2] arm64: dts: qcom: sc7280: Add gpu support Akhil P Oommen
@ 2021-08-11 14:23 ` Akhil P Oommen
2021-08-11 17:51 ` [PATCH v5 1/2] arm64: dts: qcom: sc7280: Add gpu support Stephen Boyd
1 sibling, 0 replies; 3+ messages in thread
From: Akhil P Oommen @ 2021-08-11 14:23 UTC (permalink / raw)
To: freedreno, dri-devel,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, linux-arm-msm,
Stephen Boyd, Bjorn Andersson, Rob Herring,
Manaf Meethalavalappu Pallikunhi
Cc: Jordan Crouse, Matthias Kaehlcke, Jonathan Marek,
Douglas Anderson, Rob Clark, Andy Gross, linux-kernel
From: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Add cooling-cells property and the cooling maps for the gpu thermal
zones to support GPU thermal cooling.
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
(no changes since v1)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 29 ++++++++++++++++++++++-------
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index b9006d8..cd2bbf0 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -592,7 +592,7 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
- gpu@3d00000 {
+ gpu: gpu@3d00000 {
compatible = "qcom,adreno-635.0", "qcom,adreno";
#stream-id-cells = <16>;
reg = <0 0x03d00000 0 0x40000>,
@@ -607,6 +607,7 @@
qcom,gmu = <&gmu>;
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "gfx-mem";
+ #cooling-cells = <2>;
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -2523,16 +2524,16 @@
};
gpuss0-thermal {
- polling-delay-passive = <0>;
+ polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tsens1 1>;
trips {
gpuss0_alert0: trip-point0 {
- temperature = <90000>;
+ temperature = <95000>;
hysteresis = <2000>;
- type = "hot";
+ type = "passive";
};
gpuss0_crit: gpuss0-crit {
@@ -2541,19 +2542,26 @@
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&gpuss0_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
gpuss1-thermal {
- polling-delay-passive = <0>;
+ polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&tsens1 2>;
trips {
gpuss1_alert0: trip-point0 {
- temperature = <90000>;
+ temperature = <95000>;
hysteresis = <2000>;
- type = "hot";
+ type = "passive";
};
gpuss1_crit: gpuss1-crit {
@@ -2562,6 +2570,13 @@
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&gpuss1_alert0>;
+ cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
nspss0-thermal {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v5 1/2] arm64: dts: qcom: sc7280: Add gpu support
2021-08-11 14:23 [PATCH v5 1/2] arm64: dts: qcom: sc7280: Add gpu support Akhil P Oommen
2021-08-11 14:23 ` [PATCH v5 2/2] arm64: dts: qcom: sc7280: Add gpu thermal zone cooling support Akhil P Oommen
@ 2021-08-11 17:51 ` Stephen Boyd
1 sibling, 0 replies; 3+ messages in thread
From: Stephen Boyd @ 2021-08-11 17:51 UTC (permalink / raw)
To: Akhil P Oommen, Bjorn Andersson,
Manaf Meethalavalappu Pallikunhi,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Rob Herring,
dri-devel, freedreno, linux-arm-msm
Cc: Jordan Crouse, Matthias Kaehlcke, Jonathan Marek,
Douglas Anderson, Rob Clark, Andy Gross, linux-kernel
Quoting Akhil P Oommen (2021-08-11 07:23:54)
> Add the necessary dt nodes for gpu support in sc7280.
>
> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2021-08-11 17:51 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-11 14:23 [PATCH v5 1/2] arm64: dts: qcom: sc7280: Add gpu support Akhil P Oommen
2021-08-11 14:23 ` [PATCH v5 2/2] arm64: dts: qcom: sc7280: Add gpu thermal zone cooling support Akhil P Oommen
2021-08-11 17:51 ` [PATCH v5 1/2] arm64: dts: qcom: sc7280: Add gpu support Stephen Boyd
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).