* [Patch v3 1/3] arm64: dts: hi3660: add pcie node
@ 2017-05-18 7:49 Song Xiaowei
2017-05-23 14:16 ` Rob Herring
0 siblings, 1 reply; 4+ messages in thread
From: Song Xiaowei @ 2017-05-18 7:49 UTC (permalink / raw)
To: wangzhou1, gabriele.paoloni, bhelgaas, robh+dt, mark.rutland,
xuwei5, catalin.marinas, will.deacon
Cc: linux-pci, devicetree, linux-kernel, puck.chen, songxiaowei,
guodong.xu, wangbinghui, suzhuangluan
Add PCIe node for hi3660, and add binding documentation.
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Song Xiaowei <songxiaowei@hisilicon.com>
---
.../devicetree/bindings/pci/hisilicon-pcie.txt | 52 ++++++++++++++++++++++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 +++++++++++++
2 files changed, 83 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
index a339dbb15493..71491178c86c 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
@@ -85,3 +85,55 @@ Example:
0x0 0 0 4 &mbigen_pcie0 650 4>;
status = "ok";
};
+
+
+
+HiSilicon Kirin SoC PCIe host DT description
+
+Kirin PCIe host controller is also based on Designware PCI core.
+It shares common functions with PCIe Designware core driver and inherits
+common properties defined in
+Documentation/devicetree/bindings/pci/designware-pci.txt.
+
+Additional properties are described here:
+
+Required properties
+- compatible: Should contain "hisilicon,kirin-pcie".
+- reg: Should contain rc_dbi, apb, phy, config registers location and length.
+- reg-names: Must include the following entries:
+ "dbi": controller configuration registers;
+ "apb": apb Ctrl register;
+ "phy": apb PHY register;
+ "config": PCIe configuration space registers.
+- reset-gpio: perst assert/deassert gpio
+
+Optional properties:
+- status: Either "ok" or "disabled".
+
+Kirin960 Example:
+ kirin_pcie@f4000000 {
+ compatible = "hisilicon,kirin-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF5000000 0 0x2000>;
+ reg-names = "dbi","apb","phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000 0x0 0xf6000000 0x0 0x2000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 2 &gic 0 0 0 283 4>,
+ <0x0 0 0 3 &gic 0 0 0 284 4>,
+ <0x0 0 0 4 &gic 0 0 0 285 4>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+ reset-gpio = <&gpio11 1 0 >;
+ status = "ok";
+ };
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3983086bd67b..2406a54947df 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -156,5 +156,36 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+ kirin_pcie@f4000000 {
+ compatible = "hisilicon,kirin-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>,
+ <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>,
+ <0x0 0xF5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000 0x0
+ 0xf6000000 0x0 0x2000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
+ <0x0 0 0 2 &gic 0 0 0 283 4>,
+ <0x0 0 0 3 &gic 0 0 0 284 4>,
+ <0x0 0 0 4 &gic 0 0 0 285 4>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+ reset-gpio = <&gpio11 1 0 >;
+ status = "ok";
+ };
};
};
--
2.11.GIT
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Patch v3 1/3] arm64: dts: hi3660: add pcie node
2017-05-18 7:49 [Patch v3 1/3] arm64: dts: hi3660: add pcie node Song Xiaowei
@ 2017-05-23 14:16 ` Rob Herring
[not found] ` <99B4C6BADD9E3241B25E52B02BA737C54116D35D@DGGEMA505-MBX.china.huawei.com>
0 siblings, 1 reply; 4+ messages in thread
From: Rob Herring @ 2017-05-23 14:16 UTC (permalink / raw)
To: Song Xiaowei
Cc: wangzhou1, gabriele.paoloni, bhelgaas, mark.rutland, xuwei5,
catalin.marinas, will.deacon, linux-pci, devicetree,
linux-kernel, puck.chen, guodong.xu, wangbinghui, suzhuangluan
On Thu, May 18, 2017 at 03:49:46PM +0800, Song Xiaowei wrote:
> Add PCIe node for hi3660, and add binding documentation.
>
> Cc: Guodong Xu <guodong.xu@linaro.org>
> Signed-off-by: Song Xiaowei <songxiaowei@hisilicon.com>
> ---
> .../devicetree/bindings/pci/hisilicon-pcie.txt | 52 ++++++++++++++++++++++
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 +++++++++++++
These should be separate patches.
> 2 files changed, 83 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> index a339dbb15493..71491178c86c 100644
> --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> @@ -85,3 +85,55 @@ Example:
> 0x0 0 0 4 &mbigen_pcie0 650 4>;
> status = "ok";
> };
> +
> +
> +
Why is this in the same document? If there's nothing shared, then just
do a separate doc for each SoC.
> +HiSilicon Kirin SoC PCIe host DT description
Isn't Kirin the 6220?
> +
> +Kirin PCIe host controller is also based on Designware PCI core.
> +It shares common functions with PCIe Designware core driver and inherits
> +common properties defined in
> +Documentation/devicetree/bindings/pci/designware-pci.txt.
> +
> +Additional properties are described here:
> +
> +Required properties
> +- compatible: Should contain "hisilicon,kirin-pcie".
Use the part number rather than the code name.
> +- reg: Should contain rc_dbi, apb, phy, config registers location and length.
> +- reg-names: Must include the following entries:
> + "dbi": controller configuration registers;
> + "apb": apb Ctrl register;
> + "phy": apb PHY register;
Perhaps the phy should be a separate node and use the phy binding?
> + "config": PCIe configuration space registers.
> +- reset-gpio: perst assert/deassert gpio
reset-gpios
> +
> +Optional properties:
> +- status: Either "ok" or "disabled".
Don't need to document this.
> +
> +Kirin960 Example:
> + kirin_pcie@f4000000 {
pcie@...
Build the dts with W=1 or W=2. dtc will warn for this now.
> + compatible = "hisilicon,kirin-pcie";
> + reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
> + <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF5000000 0 0x2000>;
> + reg-names = "dbi","apb","phy", "config";
> + bus-range = <0x0 0x1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges = <0x02000000 0x0 0x00000000 0x0 0xf6000000 0x0 0x2000000>;
> + num-lanes = <1>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0xf800 0 0 7>;
> + interrupt-map = <0x0 0 0 2 &gic 0 0 0 283 4>,
> + <0x0 0 0 3 &gic 0 0 0 284 4>,
> + <0x0 0 0 4 &gic 0 0 0 285 4>;
> + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
> + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
> + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
> + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
> + <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
> + clock-names = "pcie_phy_ref", "pcie_aux",
> + "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
> + reset-gpio = <&gpio11 1 0 >;
> + status = "ok";
Don't show status in examples.
> + };
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index 3983086bd67b..2406a54947df 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -156,5 +156,36 @@
> clock-names = "uartclk", "apb_pclk";
> status = "disabled";
> };
> +
> + kirin_pcie@f4000000 {
> + compatible = "hisilicon,kirin-pcie";
> + reg = <0x0 0xf4000000 0x0 0x1000>,
> + <0x0 0xff3fe000 0x0 0x1000>,
> + <0x0 0xf3f20000 0x0 0x40000>,
> + <0x0 0xF5000000 0x0 0x2000>;
> + reg-names = "dbi", "apb", "phy", "config";
> + bus-range = <0x0 0x1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges = <0x02000000 0x0 0x00000000 0x0
> + 0xf6000000 0x0 0x2000000>;
> + num-lanes = <1>;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0xf800 0 0 7>;
> + interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
> + <0x0 0 0 2 &gic 0 0 0 283 4>,
> + <0x0 0 0 3 &gic 0 0 0 284 4>,
> + <0x0 0 0 4 &gic 0 0 0 285 4>;
> + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
> + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
> + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
> + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
> + <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
> + clock-names = "pcie_phy_ref", "pcie_aux",
> + "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
> + reset-gpio = <&gpio11 1 0 >;
> + status = "ok";
> + };
> };
> };
> --
> 2.11.GIT
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: 答复: [Patch v3 1/3] arm64: dts: hi3660: add pcie node
[not found] ` <99B4C6BADD9E3241B25E52B02BA737C54116D35D@DGGEMA505-MBX.china.huawei.com>
@ 2017-05-25 12:38 ` Rob Herring
2017-05-26 1:40 ` 答复: " songxiaowei
0 siblings, 1 reply; 4+ messages in thread
From: Rob Herring @ 2017-05-25 12:38 UTC (permalink / raw)
To: songxiaowei
Cc: Wangzhou (B), Gabriele Paoloni, bhelgaas, mark.rutland, xuwei (O),
catalin.marinas, will.deacon, linux-pci, devicetree,
linux-kernel, Chenfeng (puck),
guodong.xu, Wangbinghui, Suzhuangluan
On Tue, May 23, 2017 at 8:39 PM, songxiaowei <songxiaowei@hisilicon.com> wrote:
> -----邮件原件-----
> 发件人: Rob Herring [mailto:robh@kernel.org]
> 发送时间: 2017年5月23日 22:17
> 收件人: songxiaowei
> 抄送: Wangzhou (B); Gabriele Paoloni; bhelgaas@google.com; mark.rutland@arm.com; xuwei (O); catalin.marinas@arm.com; will.deacon@arm.com; linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Chenfeng (puck); guodong.xu@linaro.org; Wangbinghui; Suzhuangluan
> 主题: Re: [Patch v3 1/3] arm64: dts: hi3660: add pcie node
>
> On Thu, May 18, 2017 at 03:49:46PM +0800, Song Xiaowei wrote:
>> Add PCIe node for hi3660, and add binding documentation.
>>
>> Cc: Guodong Xu <guodong.xu@linaro.org>
>> Signed-off-by: Song Xiaowei <songxiaowei@hisilicon.com>
>> ---
>> .../devicetree/bindings/pci/hisilicon-pcie.txt | 52 ++++++++++++++++++++++
>> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 +++++++++++++
[...]
>> + "config": PCIe configuration space registers.
>> +- reset-gpio: perst assert/deassert gpio
>
> reset-gpios
> [songxiaowei] rest-gpio is used to signal 'pcie perst': high level refers to deassert
> and low level refers to assert. So, I think ' reset-gpio: creates perst assert/deassert signal '
> would be a better choice.
What I was saying is the name should be reset-gpios, not reset-gpio.
Rob
^ permalink raw reply [flat|nested] 4+ messages in thread
* 答复: 答复: [Patch v3 1/3] arm64: dts: hi3660: add pcie node
2017-05-25 12:38 ` 答复: " Rob Herring
@ 2017-05-26 1:40 ` songxiaowei
0 siblings, 0 replies; 4+ messages in thread
From: songxiaowei @ 2017-05-26 1:40 UTC (permalink / raw)
To: Rob Herring
Cc: Wangzhou (B), Gabriele Paoloni, bhelgaas, mark.rutland, xuwei (O),
catalin.marinas, will.deacon, linux-pci, devicetree,
linux-kernel, Chenfeng (puck),
guodong.xu, Wangbinghui, Suzhuangluan
-----邮件原件-----
发件人: Rob Herring [mailto:robh@kernel.org]
发送时间: 2017年5月25日 20:39
收件人: songxiaowei
抄送: Wangzhou (B); Gabriele Paoloni; bhelgaas@google.com; mark.rutland@arm.com; xuwei (O); catalin.marinas@arm.com; will.deacon@arm.com; linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Chenfeng (puck); guodong.xu@linaro.org; Wangbinghui; Suzhuangluan
主题: Re: 答复: [Patch v3 1/3] arm64: dts: hi3660: add pcie node
On Tue, May 23, 2017 at 8:39 PM, songxiaowei <songxiaowei@hisilicon.com> wrote:
> -----邮件原件-----
> 发件人: Rob Herring [mailto:robh@kernel.org]
> 发送时间: 2017年5月23日 22:17
> 收件人: songxiaowei
> 抄送: Wangzhou (B); Gabriele Paoloni; bhelgaas@google.com; mark.rutland@arm.com; xuwei (O); catalin.marinas@arm.com; will.deacon@arm.com; linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Chenfeng (puck); guodong.xu@linaro.org; Wangbinghui; Suzhuangluan
> 主题: Re: [Patch v3 1/3] arm64: dts: hi3660: add pcie node
>
> On Thu, May 18, 2017 at 03:49:46PM +0800, Song Xiaowei wrote:
>> Add PCIe node for hi3660, and add binding documentation.
>>
>> Cc: Guodong Xu <guodong.xu@linaro.org>
>> Signed-off-by: Song Xiaowei <songxiaowei@hisilicon.com>
>> ---
>> .../devicetree/bindings/pci/hisilicon-pcie.txt | 52 ++++++++++++++++++++++
>> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 +++++++++++++
[...]
>> + "config": PCIe configuration space registers.
>> +- reset-gpio: perst assert/deassert gpio
>
> reset-gpios
> [songxiaowei] rest-gpio is used to signal 'pcie perst': high level refers to deassert
> and low level refers to assert. So, I think ' reset-gpio: creates perst assert/deassert signal '
> would be a better choice.
What I was saying is the name should be reset-gpios, not reset-gpio.
[songxiaowei] Ok, I'll fix it. In fact, perst signal only use one line, so reset-gpios contains only one gpio.
Rob
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-05-26 1:41 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-05-18 7:49 [Patch v3 1/3] arm64: dts: hi3660: add pcie node Song Xiaowei
2017-05-23 14:16 ` Rob Herring
[not found] ` <99B4C6BADD9E3241B25E52B02BA737C54116D35D@DGGEMA505-MBX.china.huawei.com>
2017-05-25 12:38 ` 答复: " Rob Herring
2017-05-26 1:40 ` 答复: " songxiaowei
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