* [PATCH] riscv: Setup exception vector for K210 properly
@ 2020-08-11 6:36 Qiu Wenbo
2020-08-11 6:42 ` Damien Le Moal
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Qiu Wenbo @ 2020-08-11 6:36 UTC (permalink / raw)
To: Palmer Dabbelt, Paul Walmsley, linux-riscv
Cc: Qiu Wenbo, Albert Ou, Atish Patra, Anup Patel, Guo Ren, Zong Li,
Greentime Hu, Vincent Chen, Damien Le Moal, linux-kernel
Exception vector is missing on nommu platform and it is a big issue.
This patch is tested in Sipeed MAIX Bit Dev Board.
Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn>
---
arch/riscv/kernel/smpboot.c | 1 +
arch/riscv/kernel/traps.c | 11 ++++++++++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 356825a57551..23cde0ceb39d 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -154,6 +154,7 @@ asmlinkage __visible void smp_callin(void)
mmgrab(mm);
current->active_mm = mm;
+ trap_init();
notify_cpu_starting(curr_cpuid);
update_siblings_masks(curr_cpuid);
set_cpu_online(curr_cpuid, 1);
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
index ad14f4466d92..a390239818ae 100644
--- a/arch/riscv/kernel/traps.c
+++ b/arch/riscv/kernel/traps.c
@@ -174,7 +174,16 @@ int is_valid_bugaddr(unsigned long pc)
}
#endif /* CONFIG_GENERIC_BUG */
-/* stvec & scratch is already set from head.S */
+/* stvec & scratch is already set from head.S when mmu is enabled */
void trap_init(void)
{
+#ifndef CONFIG_MMU
+ /*
+ * Set sup0 scratch register to 0, indicating to exception vector
+ * that we are presently executing in the kernel
+ */
+ csr_write(CSR_SCRATCH, 0);
+ /* Set the exception vector address */
+ csr_write(CSR_TVEC, &handle_exception);
+#endif
}
--
2.28.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: Setup exception vector for K210 properly
2020-08-11 6:36 [PATCH] riscv: Setup exception vector for K210 properly Qiu Wenbo
@ 2020-08-11 6:42 ` Damien Le Moal
2020-08-11 7:05 ` 邱文博
2020-08-11 6:43 ` Damien Le Moal
2020-08-11 8:40 ` Anup Patel
2 siblings, 1 reply; 10+ messages in thread
From: Damien Le Moal @ 2020-08-11 6:42 UTC (permalink / raw)
To: Qiu Wenbo, Palmer Dabbelt, Paul Walmsley, linux-riscv
Cc: Albert Ou, Atish Patra, Anup Patel, Guo Ren, Zong Li,
Greentime Hu, Vincent Chen, linux-kernel
On 2020/08/11 15:38, Qiu Wenbo wrote:
> Exception vector is missing on nommu platform and it is a big issue.
> This patch is tested in Sipeed MAIX Bit Dev Board.
>
> Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
> Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn>
> ---
> arch/riscv/kernel/smpboot.c | 1 +
> arch/riscv/kernel/traps.c | 11 ++++++++++-
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> index 356825a57551..23cde0ceb39d 100644
> --- a/arch/riscv/kernel/smpboot.c
> +++ b/arch/riscv/kernel/smpboot.c
> @@ -154,6 +154,7 @@ asmlinkage __visible void smp_callin(void)
> mmgrab(mm);
> current->active_mm = mm;
>
> + trap_init();
> notify_cpu_starting(curr_cpuid);
> update_siblings_masks(curr_cpuid);
> set_cpu_online(curr_cpuid, 1);
> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> index ad14f4466d92..a390239818ae 100644
> --- a/arch/riscv/kernel/traps.c
> +++ b/arch/riscv/kernel/traps.c
> @@ -174,7 +174,16 @@ int is_valid_bugaddr(unsigned long pc)
> }
> #endif /* CONFIG_GENERIC_BUG */
>
> -/* stvec & scratch is already set from head.S */
> +/* stvec & scratch is already set from head.S when mmu is enabled */
> void trap_init(void)
> {
> +#ifndef CONFIG_MMU
> + /*
> + * Set sup0 scratch register to 0, indicating to exception vector
> + * that we are presently executing in the kernel
> + */
> + csr_write(CSR_SCRATCH, 0);
> + /* Set the exception vector address */
> + csr_write(CSR_TVEC, &handle_exception);
> +#endif
> }
>
Looks OK to me. But out of curiosity, how did you trigger a problem ? I never
got any weird exceptions with my busybox userspace.
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: Setup exception vector for K210 properly
2020-08-11 6:36 [PATCH] riscv: Setup exception vector for K210 properly Qiu Wenbo
2020-08-11 6:42 ` Damien Le Moal
@ 2020-08-11 6:43 ` Damien Le Moal
2020-08-11 8:40 ` Anup Patel
2 siblings, 0 replies; 10+ messages in thread
From: Damien Le Moal @ 2020-08-11 6:43 UTC (permalink / raw)
To: Qiu Wenbo, Palmer Dabbelt, Paul Walmsley, linux-riscv
Cc: Albert Ou, Atish Patra, Anup Patel, Guo Ren, Zong Li,
Greentime Hu, Vincent Chen, linux-kernel
On 2020/08/11 15:38, Qiu Wenbo wrote:
> Exception vector is missing on nommu platform and it is a big issue.
> This patch is tested in Sipeed MAIX Bit Dev Board.
>
> Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
I think this needs a "Cc: stable@vger.kernel.org #5.8" too.
> Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn>
> ---
> arch/riscv/kernel/smpboot.c | 1 +
> arch/riscv/kernel/traps.c | 11 ++++++++++-
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> index 356825a57551..23cde0ceb39d 100644
> --- a/arch/riscv/kernel/smpboot.c
> +++ b/arch/riscv/kernel/smpboot.c
> @@ -154,6 +154,7 @@ asmlinkage __visible void smp_callin(void)
> mmgrab(mm);
> current->active_mm = mm;
>
> + trap_init();
> notify_cpu_starting(curr_cpuid);
> update_siblings_masks(curr_cpuid);
> set_cpu_online(curr_cpuid, 1);
> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> index ad14f4466d92..a390239818ae 100644
> --- a/arch/riscv/kernel/traps.c
> +++ b/arch/riscv/kernel/traps.c
> @@ -174,7 +174,16 @@ int is_valid_bugaddr(unsigned long pc)
> }
> #endif /* CONFIG_GENERIC_BUG */
>
> -/* stvec & scratch is already set from head.S */
> +/* stvec & scratch is already set from head.S when mmu is enabled */
> void trap_init(void)
> {
> +#ifndef CONFIG_MMU
> + /*
> + * Set sup0 scratch register to 0, indicating to exception vector
> + * that we are presently executing in the kernel
> + */
> + csr_write(CSR_SCRATCH, 0);
> + /* Set the exception vector address */
> + csr_write(CSR_TVEC, &handle_exception);
> +#endif
> }
>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: Re: [PATCH] riscv: Setup exception vector for K210 properly
2020-08-11 6:42 ` Damien Le Moal
@ 2020-08-11 7:05 ` 邱文博
2020-08-11 7:44 ` Damien Le Moal
0 siblings, 1 reply; 10+ messages in thread
From: 邱文博 @ 2020-08-11 7:05 UTC (permalink / raw)
To: Damien Le Moal
Cc: Palmer Dabbelt, Paul Walmsley, linux-riscv, Albert Ou,
Atish Patra, Anup Patel, Guo Ren, Zong Li, Greentime Hu,
Vincent Chen, linux-kernel
The serial port did not print anything after early console.
[ 0.000000] Sorting __ex_table...
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] Memory: 6480K/8192K available (1024K kernel code, 111K rwdata, 170K rodata, 101K init, 97K bss, 1712K reserved, 0K cma-reserved)
[ 0.000000] rcu: Hierarchical RCU implementation.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] riscv-intc: 64 local interrupts mapped
[ 0.000000] plic: interrupt-controller@c000000: mapped 65 interrupts with 2 handlers for 4 contexts.
[ 0.000000] random: get_random_bytes called from 0x00000000800019a4 with crng_init=0
[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0]
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x3990be68b, max_idle_ns: 881590404272 ns
[ 0.000015] sched_clock: 64 bits at 7MHz, resolution 128ns, wraps every 4398046511054ns
[ 0.008254] Console: colour dummy device 80x25
> -----原始邮件-----
> 发件人: "Damien Le Moal" <damien.lemoal@wdc.com>
> 发送时间: 2020-08-11 14:42:15 (星期二)
> 收件人: "Qiu Wenbo" <qiuwenbo@phytium.com.cn>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>
> 抄送: "Albert Ou" <aou@eecs.berkeley.edu>, "Atish Patra" <atish.patra@wdc.com>, "Anup
> Patel" <anup@brainfault.org>, "Guo Ren" <guoren@linux.alibaba.com>, "Zong Li" <zong.li@sifive.com>, "Greentime Hu" <greentime.hu@sifive.com>, "Vincent Chen" <vincent.chen@sifive.com>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
> 主题: Re: [PATCH] riscv: Setup exception vector for K210 properly
>
> On 2020/08/11 15:38, Qiu Wenbo wrote:
> > Exception vector is missing on nommu platform and it is a big issue.
> > This patch is tested in Sipeed MAIX Bit Dev Board.
> >
> > Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
> > Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn>
> > ---
> > arch/riscv/kernel/smpboot.c | 1 +
> > arch/riscv/kernel/traps.c | 11 ++++++++++-
> > 2 files changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> > index 356825a57551..23cde0ceb39d 100644
> > --- a/arch/riscv/kernel/smpboot.c
> > +++ b/arch/riscv/kernel/smpboot.c
> > @@ -154,6 +154,7 @@ asmlinkage __visible void smp_callin(void)
> > mmgrab(mm);
> > current->active_mm = mm;
> >
> > + trap_init();
> > notify_cpu_starting(curr_cpuid);
> > update_siblings_masks(curr_cpuid);
> > set_cpu_online(curr_cpuid, 1);
> > diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> > index ad14f4466d92..a390239818ae 100644
> > --- a/arch/riscv/kernel/traps.c
> > +++ b/arch/riscv/kernel/traps.c
> > @@ -174,7 +174,16 @@ int is_valid_bugaddr(unsigned long pc)
> > }
> > #endif /* CONFIG_GENERIC_BUG */
> >
> > -/* stvec & scratch is already set from head.S */
> > +/* stvec & scratch is already set from head.S when mmu is enabled */
> > void trap_init(void)
> > {
> > +#ifndef CONFIG_MMU
> > + /*
> > + * Set sup0 scratch register to 0, indicating to exception vector
> > + * that we are presently executing in the kernel
> > + */
> > + csr_write(CSR_SCRATCH, 0);
> > + /* Set the exception vector address */
> > + csr_write(CSR_TVEC, &handle_exception);
> > +#endif
> > }
> >
>
> Looks OK to me. But out of curiosity, how did you trigger a problem ? I never
> got any weird exceptions with my busybox userspace.
>
> --
> Damien Le Moal
> Western Digital Research
</qiuwenbo@phytium.com.cn></linux-kernel@vger.kernel.org></vincent.chen@sifive.com></greentime.hu@sifive.com></zong.li@sifive.com></guoren@linux.alibaba.com></anup@brainfault.org></atish.patra@wdc.com></aou@eecs.berkeley.edu></linux-riscv@lists.infradead.org></paul.walmsley@sifive.com></palmer@dabbelt.com></qiuwenbo@phytium.com.cn></damien.lemoal@wdc.com>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: Setup exception vector for K210 properly
2020-08-11 7:05 ` 邱文博
@ 2020-08-11 7:44 ` Damien Le Moal
0 siblings, 0 replies; 10+ messages in thread
From: Damien Le Moal @ 2020-08-11 7:44 UTC (permalink / raw)
To: 邱文博
Cc: Palmer Dabbelt, Paul Walmsley, linux-riscv, Albert Ou,
Atish Patra, Anup Patel, Guo Ren, Zong Li, Greentime Hu,
Vincent Chen, linux-kernel
On 2020/08/11 16:06, 邱文博 wrote:
> The serial port did not print anything after early console.
>
> [ 0.000000] Sorting __ex_table...
> [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
> [ 0.000000] Memory: 6480K/8192K available (1024K kernel code, 111K rwdata, 170K rodata, 101K init, 97K bss, 1712K reserved, 0K cma-reserved)
> [ 0.000000] rcu: Hierarchical RCU implementation.
> [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
> [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
> [ 0.000000] riscv-intc: 64 local interrupts mapped
> [ 0.000000] plic: interrupt-controller@c000000: mapped 65 interrupts with 2 handlers for 4 contexts.
> [ 0.000000] random: get_random_bytes called from 0x00000000800019a4 with crng_init=0
> [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0]
> [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x3990be68b, max_idle_ns: 881590404272 ns
> [ 0.000015] sched_clock: 64 bits at 7MHz, resolution 128ns, wraps every 4398046511054ns
> [ 0.008254] Console: colour dummy device 80x25
Interesting. Never saw that happening... Thanks !
>
>
>
> > -----原始邮件-----
> > 发件人: "Damien Le Moal" <damien.lemoal@wdc.com>
> > 发送时间: 2020-08-11 14:42:15 (星期二)
> > 收件人: "Qiu Wenbo" <qiuwenbo@phytium.com.cn>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Paul Walmsley" <paul.walmsley@sifive.com>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>
> > 抄送: "Albert Ou" <aou@eecs.berkeley.edu>, "Atish Patra" <atish.patra@wdc.com>, "Anup
> > Patel" <anup@brainfault.org>, "Guo Ren" <guoren@linux.alibaba.com>, "Zong Li" <zong.li@sifive.com>, "Greentime Hu" <greentime.hu@sifive.com>, "Vincent Chen" <vincent.chen@sifive.com>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
> > 主题: Re: [PATCH] riscv: Setup exception vector for K210 properly
> >
> > On 2020/08/11 15:38, Qiu Wenbo wrote:
> > > Exception vector is missing on nommu platform and it is a big issue.
> > > This patch is tested in Sipeed MAIX Bit Dev Board.
> > >
> > > Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
> > > Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn>
> > > ---
> > > arch/riscv/kernel/smpboot.c | 1 +
> > > arch/riscv/kernel/traps.c | 11 ++++++++++-
> > > 2 files changed, 11 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> > > index 356825a57551..23cde0ceb39d 100644
> > > --- a/arch/riscv/kernel/smpboot.c
> > > +++ b/arch/riscv/kernel/smpboot.c
> > > @@ -154,6 +154,7 @@ asmlinkage __visible void smp_callin(void)
> > > mmgrab(mm);
> > > current->active_mm = mm;
> > >
> > > + trap_init();
> > > notify_cpu_starting(curr_cpuid);
> > > update_siblings_masks(curr_cpuid);
> > > set_cpu_online(curr_cpuid, 1);
> > > diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> > > index ad14f4466d92..a390239818ae 100644
> > > --- a/arch/riscv/kernel/traps.c
> > > +++ b/arch/riscv/kernel/traps.c
> > > @@ -174,7 +174,16 @@ int is_valid_bugaddr(unsigned long pc)
> > > }
> > > #endif /* CONFIG_GENERIC_BUG */
> > >
> > > -/* stvec & scratch is already set from head.S */
> > > +/* stvec & scratch is already set from head.S when mmu is enabled */
> > > void trap_init(void)
> > > {
> > > +#ifndef CONFIG_MMU
> > > + /*
> > > + * Set sup0 scratch register to 0, indicating to exception vector
> > > + * that we are presently executing in the kernel
> > > + */
> > > + csr_write(CSR_SCRATCH, 0);
> > > + /* Set the exception vector address */
> > > + csr_write(CSR_TVEC, &handle_exception);
> > > +#endif
> > > }
> > >
> >
> > Looks OK to me. But out of curiosity, how did you trigger a problem ? I never
> > got any weird exceptions with my busybox userspace.
> >
> > --
> > Damien Le Moal
> > Western Digital Research
> </qiuwenbo@phytium.com.cn></linux-kernel@vger.kernel.org></vincent.chen@sifive.com></greentime.hu@sifive.com></zong.li@sifive.com></guoren@linux.alibaba.com></anup@brainfault.org></atish.patra@wdc.com></aou@eecs.berkeley.edu></linux-riscv@lists.infradead.org></paul.walmsley@sifive.com></palmer@dabbelt.com></qiuwenbo@phytium.com.cn></damien.lemoal@wdc.com>
>
>
>
>
>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: Setup exception vector for K210 properly
2020-08-11 6:36 [PATCH] riscv: Setup exception vector for K210 properly Qiu Wenbo
2020-08-11 6:42 ` Damien Le Moal
2020-08-11 6:43 ` Damien Le Moal
@ 2020-08-11 8:40 ` Anup Patel
2020-08-11 18:45 ` Atish Patra
2 siblings, 1 reply; 10+ messages in thread
From: Anup Patel @ 2020-08-11 8:40 UTC (permalink / raw)
To: Qiu Wenbo
Cc: Palmer Dabbelt, Paul Walmsley, linux-riscv, Albert Ou,
Atish Patra, Guo Ren, Zong Li, Greentime Hu, Vincent Chen,
Damien Le Moal, linux-kernel@vger.kernel.org List
On Tue, Aug 11, 2020 at 12:07 PM Qiu Wenbo <qiuwenbo@phytium.com.cn> wrote:
>
> Exception vector is missing on nommu platform and it is a big issue.
> This patch is tested in Sipeed MAIX Bit Dev Board.
>
> Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
> Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn>
> ---
> arch/riscv/kernel/smpboot.c | 1 +
> arch/riscv/kernel/traps.c | 11 ++++++++++-
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> index 356825a57551..23cde0ceb39d 100644
> --- a/arch/riscv/kernel/smpboot.c
> +++ b/arch/riscv/kernel/smpboot.c
> @@ -154,6 +154,7 @@ asmlinkage __visible void smp_callin(void)
> mmgrab(mm);
> current->active_mm = mm;
>
> + trap_init();
> notify_cpu_starting(curr_cpuid);
> update_siblings_masks(curr_cpuid);
> set_cpu_online(curr_cpuid, 1);
> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> index ad14f4466d92..a390239818ae 100644
> --- a/arch/riscv/kernel/traps.c
> +++ b/arch/riscv/kernel/traps.c
> @@ -174,7 +174,16 @@ int is_valid_bugaddr(unsigned long pc)
> }
> #endif /* CONFIG_GENERIC_BUG */
>
> -/* stvec & scratch is already set from head.S */
> +/* stvec & scratch is already set from head.S when mmu is enabled */
> void trap_init(void)
> {
> +#ifndef CONFIG_MMU
> + /*
> + * Set sup0 scratch register to 0, indicating to exception vector
> + * that we are presently executing in the kernel
> + */
> + csr_write(CSR_SCRATCH, 0);
> + /* Set the exception vector address */
> + csr_write(CSR_TVEC, &handle_exception);
> +#endif
> }
> --
> 2.28.0
>
This issue seems to be only on the latest master branch of
Linux stable tree so this fix need not be a stable fix.
For MMU kernel, the CSR_TVEC is setup in relocate() function
called from secondary_start_common() function of head.S
For NoMMU kernel, we should set CSR_TVEC directly in
secondary_start_common() function as "#else" case of the
"#ifdef CONFIG_MMU".
Regards,
Anup
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: Setup exception vector for K210 properly
2020-08-11 8:40 ` Anup Patel
@ 2020-08-11 18:45 ` Atish Patra
2020-08-12 1:09 ` Qiu Wenbo
2020-08-12 1:57 ` Anup Patel
0 siblings, 2 replies; 10+ messages in thread
From: Atish Patra @ 2020-08-11 18:45 UTC (permalink / raw)
To: Anup Patel
Cc: Qiu Wenbo, Damien Le Moal, Guo Ren, Vincent Chen,
linux-kernel@vger.kernel.org List, Atish Patra, Albert Ou,
Palmer Dabbelt, Zong Li, Paul Walmsley, Greentime Hu,
linux-riscv
On Tue, Aug 11, 2020 at 1:41 AM Anup Patel <anup@brainfault.org> wrote:
>
> On Tue, Aug 11, 2020 at 12:07 PM Qiu Wenbo <qiuwenbo@phytium.com.cn> wrote:
> >
> > Exception vector is missing on nommu platform and it is a big issue.
> > This patch is tested in Sipeed MAIX Bit Dev Board.
> >
> > Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
> > Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn>
Thanks for testing it on the kendryte board.
> > ---
> > arch/riscv/kernel/smpboot.c | 1 +
> > arch/riscv/kernel/traps.c | 11 ++++++++++-
> > 2 files changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> > index 356825a57551..23cde0ceb39d 100644
> > --- a/arch/riscv/kernel/smpboot.c
> > +++ b/arch/riscv/kernel/smpboot.c
> > @@ -154,6 +154,7 @@ asmlinkage __visible void smp_callin(void)
> > mmgrab(mm);
> > current->active_mm = mm;
> >
> > + trap_init();
> > notify_cpu_starting(curr_cpuid);
> > update_siblings_masks(curr_cpuid);
> > set_cpu_online(curr_cpuid, 1);
> > diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> > index ad14f4466d92..a390239818ae 100644
> > --- a/arch/riscv/kernel/traps.c
> > +++ b/arch/riscv/kernel/traps.c
> > @@ -174,7 +174,16 @@ int is_valid_bugaddr(unsigned long pc)
> > }
> > #endif /* CONFIG_GENERIC_BUG */
> >
> > -/* stvec & scratch is already set from head.S */
> > +/* stvec & scratch is already set from head.S when mmu is enabled */
> > void trap_init(void)
> > {
> > +#ifndef CONFIG_MMU
> > + /*
> > + * Set sup0 scratch register to 0, indicating to exception vector
> > + * that we are presently executing in the kernel
> > + */
> > + csr_write(CSR_SCRATCH, 0);
> > + /* Set the exception vector address */
> > + csr_write(CSR_TVEC, &handle_exception);
> > +#endif
> > }
> > --
> > 2.28.0
> >
>
> This issue seems to be only on the latest master branch of
> Linux stable tree so this fix need not be a stable fix.
>
> For MMU kernel, the CSR_TVEC is setup in relocate() function
> called from secondary_start_common() function of head.S
>
> For NoMMU kernel, we should set CSR_TVEC directly in
> secondary_start_common() function as "#else" case of the
> "#ifdef CONFIG_MMU".
>
That would enable the trap only for secondary harts. But the exception
vector on boot hart
is still uninitialized. How about this change ?
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index d0c5c316e9bb..7822054dbd88 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -77,16 +77,6 @@ relocate:
csrw CSR_SATP, a0
.align 2
1:
- /* Set trap vector to exception handler */
- la a0, handle_exception
- csrw CSR_TVEC, a0
-
- /*
- * Set sup0 scratch register to 0, indicating to exception vector that
- * we are presently executing in kernel.
- */
- csrw CSR_SCRATCH, zero
-
/* Reload the global pointer */
.option push
.option norelax
@@ -144,9 +134,23 @@ secondary_start_common:
la a0, swapper_pg_dir
call relocate
#endif
+ call setup_trap_vector
tail smp_callin
#endif /* CONFIG_SMP */
+.align 2
+setup_trap_vector:
+ /* Set trap vector to exception handler */
+ la a0, handle_exception
+ csrw CSR_TVEC, a0
+
+ /*
+ * Set sup0 scratch register to 0, indicating to exception vector that
+ * we are presently executing in kernel.
+ */
+ csrw CSR_SCRATCH, zero
+ ret
+
.Lsecondary_park:
/* We lack SMP support or have too many harts, so park this hart */
wfi
@@ -240,6 +244,7 @@ clear_bss_done:
call relocate
#endif /* CONFIG_MMU */
+ call setup_trap_vector
/* Restore C environment */
la tp, init_task
sw zero, TASK_TI_CPU(tp)
> Regards,
> Anup
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
--
Regards,
Atish
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: Setup exception vector for K210 properly
2020-08-11 18:45 ` Atish Patra
@ 2020-08-12 1:09 ` Qiu Wenbo
2020-08-12 1:57 ` Anup Patel
1 sibling, 0 replies; 10+ messages in thread
From: Qiu Wenbo @ 2020-08-12 1:09 UTC (permalink / raw)
To: Atish Patra, Anup Patel
Cc: Damien Le Moal, Guo Ren, Vincent Chen,
linux-kernel@vger.kernel.org List, Atish Patra, Albert Ou,
Palmer Dabbelt, Zong Li, Paul Walmsley, Greentime Hu,
linux-riscv
That is a more reasonable approach.
On 8/12/20 2:45 AM, Atish Patra wrote:
> On Tue, Aug 11, 2020 at 1:41 AM Anup Patel <anup@brainfault.org> wrote:
>> On Tue, Aug 11, 2020 at 12:07 PM Qiu Wenbo <qiuwenbo@phytium.com.cn> wrote:
>>> Exception vector is missing on nommu platform and it is a big issue.
>>> This patch is tested in Sipeed MAIX Bit Dev Board.
>>>
>>> Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
>>> Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn>
> Thanks for testing it on the kendryte board.
>
>>> ---
>>> arch/riscv/kernel/smpboot.c | 1 +
>>> arch/riscv/kernel/traps.c | 11 ++++++++++-
>>> 2 files changed, 11 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
>>> index 356825a57551..23cde0ceb39d 100644
>>> --- a/arch/riscv/kernel/smpboot.c
>>> +++ b/arch/riscv/kernel/smpboot.c
>>> @@ -154,6 +154,7 @@ asmlinkage __visible void smp_callin(void)
>>> mmgrab(mm);
>>> current->active_mm = mm;
>>>
>>> + trap_init();
>>> notify_cpu_starting(curr_cpuid);
>>> update_siblings_masks(curr_cpuid);
>>> set_cpu_online(curr_cpuid, 1);
>>> diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
>>> index ad14f4466d92..a390239818ae 100644
>>> --- a/arch/riscv/kernel/traps.c
>>> +++ b/arch/riscv/kernel/traps.c
>>> @@ -174,7 +174,16 @@ int is_valid_bugaddr(unsigned long pc)
>>> }
>>> #endif /* CONFIG_GENERIC_BUG */
>>>
>>> -/* stvec & scratch is already set from head.S */
>>> +/* stvec & scratch is already set from head.S when mmu is enabled */
>>> void trap_init(void)
>>> {
>>> +#ifndef CONFIG_MMU
>>> + /*
>>> + * Set sup0 scratch register to 0, indicating to exception vector
>>> + * that we are presently executing in the kernel
>>> + */
>>> + csr_write(CSR_SCRATCH, 0);
>>> + /* Set the exception vector address */
>>> + csr_write(CSR_TVEC, &handle_exception);
>>> +#endif
>>> }
>>> --
>>> 2.28.0
>>>
>> This issue seems to be only on the latest master branch of
>> Linux stable tree so this fix need not be a stable fix.
>>
>> For MMU kernel, the CSR_TVEC is setup in relocate() function
>> called from secondary_start_common() function of head.S
>>
>> For NoMMU kernel, we should set CSR_TVEC directly in
>> secondary_start_common() function as "#else" case of the
>> "#ifdef CONFIG_MMU".
>>
> That would enable the trap only for secondary harts. But the exception
> vector on boot hart
> is still uninitialized. How about this change ?
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index d0c5c316e9bb..7822054dbd88 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -77,16 +77,6 @@ relocate:
> csrw CSR_SATP, a0
> .align 2
> 1:
> - /* Set trap vector to exception handler */
> - la a0, handle_exception
> - csrw CSR_TVEC, a0
> -
> - /*
> - * Set sup0 scratch register to 0, indicating to exception vector that
> - * we are presently executing in kernel.
> - */
> - csrw CSR_SCRATCH, zero
> -
> /* Reload the global pointer */
> .option push
> .option norelax
> @@ -144,9 +134,23 @@ secondary_start_common:
> la a0, swapper_pg_dir
> call relocate
> #endif
> + call setup_trap_vector
> tail smp_callin
> #endif /* CONFIG_SMP */
>
> +.align 2
> +setup_trap_vector:
> + /* Set trap vector to exception handler */
> + la a0, handle_exception
> + csrw CSR_TVEC, a0
> +
> + /*
> + * Set sup0 scratch register to 0, indicating to exception vector that
> + * we are presently executing in kernel.
> + */
> + csrw CSR_SCRATCH, zero
> + ret
> +
> .Lsecondary_park:
> /* We lack SMP support or have too many harts, so park this hart */
> wfi
> @@ -240,6 +244,7 @@ clear_bss_done:
> call relocate
> #endif /* CONFIG_MMU */
>
> + call setup_trap_vector
> /* Restore C environment */
> la tp, init_task
> sw zero, TASK_TI_CPU(tp)
>
>
>> Regards,
>> Anup
>>
>> _______________________________________________
>> linux-riscv mailing list
>> linux-riscv@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-riscv
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: Setup exception vector for K210 properly
2020-08-11 18:45 ` Atish Patra
2020-08-12 1:09 ` Qiu Wenbo
@ 2020-08-12 1:57 ` Anup Patel
2020-08-12 7:41 ` Atish Patra
1 sibling, 1 reply; 10+ messages in thread
From: Anup Patel @ 2020-08-12 1:57 UTC (permalink / raw)
To: Atish Patra
Cc: Qiu Wenbo, Damien Le Moal, Guo Ren, Vincent Chen,
linux-kernel@vger.kernel.org List, Atish Patra, Albert Ou,
Palmer Dabbelt, Zong Li, Paul Walmsley, Greentime Hu,
linux-riscv
On Wed, Aug 12, 2020 at 12:16 AM Atish Patra <atishp@atishpatra.org> wrote:
>
> On Tue, Aug 11, 2020 at 1:41 AM Anup Patel <anup@brainfault.org> wrote:
> >
> > On Tue, Aug 11, 2020 at 12:07 PM Qiu Wenbo <qiuwenbo@phytium.com.cn> wrote:
> > >
> > > Exception vector is missing on nommu platform and it is a big issue.
> > > This patch is tested in Sipeed MAIX Bit Dev Board.
> > >
> > > Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
> > > Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn>
>
> Thanks for testing it on the kendryte board.
>
> > > ---
> > > arch/riscv/kernel/smpboot.c | 1 +
> > > arch/riscv/kernel/traps.c | 11 ++++++++++-
> > > 2 files changed, 11 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> > > index 356825a57551..23cde0ceb39d 100644
> > > --- a/arch/riscv/kernel/smpboot.c
> > > +++ b/arch/riscv/kernel/smpboot.c
> > > @@ -154,6 +154,7 @@ asmlinkage __visible void smp_callin(void)
> > > mmgrab(mm);
> > > current->active_mm = mm;
> > >
> > > + trap_init();
> > > notify_cpu_starting(curr_cpuid);
> > > update_siblings_masks(curr_cpuid);
> > > set_cpu_online(curr_cpuid, 1);
> > > diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> > > index ad14f4466d92..a390239818ae 100644
> > > --- a/arch/riscv/kernel/traps.c
> > > +++ b/arch/riscv/kernel/traps.c
> > > @@ -174,7 +174,16 @@ int is_valid_bugaddr(unsigned long pc)
> > > }
> > > #endif /* CONFIG_GENERIC_BUG */
> > >
> > > -/* stvec & scratch is already set from head.S */
> > > +/* stvec & scratch is already set from head.S when mmu is enabled */
> > > void trap_init(void)
> > > {
> > > +#ifndef CONFIG_MMU
> > > + /*
> > > + * Set sup0 scratch register to 0, indicating to exception vector
> > > + * that we are presently executing in the kernel
> > > + */
> > > + csr_write(CSR_SCRATCH, 0);
> > > + /* Set the exception vector address */
> > > + csr_write(CSR_TVEC, &handle_exception);
> > > +#endif
> > > }
> > > --
> > > 2.28.0
> > >
> >
> > This issue seems to be only on the latest master branch of
> > Linux stable tree so this fix need not be a stable fix.
> >
> > For MMU kernel, the CSR_TVEC is setup in relocate() function
> > called from secondary_start_common() function of head.S
> >
> > For NoMMU kernel, we should set CSR_TVEC directly in
> > secondary_start_common() function as "#else" case of the
> > "#ifdef CONFIG_MMU".
> >
>
> That would enable the trap only for secondary harts. But the exception
> vector on boot hart
> is still uninitialized. How about this change ?
>
> diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> index d0c5c316e9bb..7822054dbd88 100644
> --- a/arch/riscv/kernel/head.S
> +++ b/arch/riscv/kernel/head.S
> @@ -77,16 +77,6 @@ relocate:
> csrw CSR_SATP, a0
> .align 2
> 1:
> - /* Set trap vector to exception handler */
> - la a0, handle_exception
> - csrw CSR_TVEC, a0
> -
> - /*
> - * Set sup0 scratch register to 0, indicating to exception vector that
> - * we are presently executing in kernel.
> - */
> - csrw CSR_SCRATCH, zero
> -
Instead of having no trap vector setup here, we should
at least have dummy trap vector (just like original code).
/* Set trap vector to spin forever to help debug */
la a0, .Lsecondary_park
csrw CSR_TVEC, a0
> /* Reload the global pointer */
> .option push
> .option norelax
> @@ -144,9 +134,23 @@ secondary_start_common:
> la a0, swapper_pg_dir
> call relocate
> #endif
> + call setup_trap_vector
> tail smp_callin
> #endif /* CONFIG_SMP */
>
> +.align 2
> +setup_trap_vector:
> + /* Set trap vector to exception handler */
> + la a0, handle_exception
> + csrw CSR_TVEC, a0
> +
> + /*
> + * Set sup0 scratch register to 0, indicating to exception vector that
> + * we are presently executing in kernel.
> + */
> + csrw CSR_SCRATCH, zero
> + ret
> +
> .Lsecondary_park:
> /* We lack SMP support or have too many harts, so park this hart */
> wfi
> @@ -240,6 +244,7 @@ clear_bss_done:
> call relocate
> #endif /* CONFIG_MMU */
>
> + call setup_trap_vector
> /* Restore C environment */
> la tp, init_task
> sw zero, TASK_TI_CPU(tp)
Apart from above, this looks good.
Regards,
Anup
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] riscv: Setup exception vector for K210 properly
2020-08-12 1:57 ` Anup Patel
@ 2020-08-12 7:41 ` Atish Patra
0 siblings, 0 replies; 10+ messages in thread
From: Atish Patra @ 2020-08-12 7:41 UTC (permalink / raw)
To: Anup Patel
Cc: Qiu Wenbo, Damien Le Moal, Guo Ren, Vincent Chen,
linux-kernel@vger.kernel.org List, Atish Patra, Albert Ou,
Palmer Dabbelt, Zong Li, Paul Walmsley, Greentime Hu,
linux-riscv
On Tue, Aug 11, 2020 at 6:57 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Wed, Aug 12, 2020 at 12:16 AM Atish Patra <atishp@atishpatra.org> wrote:
> >
> > On Tue, Aug 11, 2020 at 1:41 AM Anup Patel <anup@brainfault.org> wrote:
> > >
> > > On Tue, Aug 11, 2020 at 12:07 PM Qiu Wenbo <qiuwenbo@phytium.com.cn> wrote:
> > > >
> > > > Exception vector is missing on nommu platform and it is a big issue.
> > > > This patch is tested in Sipeed MAIX Bit Dev Board.
> > > >
> > > > Fixes: 79b1feba5455 ("RISC-V: Setup exception vector early")
> > > > Signed-off-by: Qiu Wenbo <qiuwenbo@phytium.com.cn>
> >
> > Thanks for testing it on the kendryte board.
> >
> > > > ---
> > > > arch/riscv/kernel/smpboot.c | 1 +
> > > > arch/riscv/kernel/traps.c | 11 ++++++++++-
> > > > 2 files changed, 11 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
> > > > index 356825a57551..23cde0ceb39d 100644
> > > > --- a/arch/riscv/kernel/smpboot.c
> > > > +++ b/arch/riscv/kernel/smpboot.c
> > > > @@ -154,6 +154,7 @@ asmlinkage __visible void smp_callin(void)
> > > > mmgrab(mm);
> > > > current->active_mm = mm;
> > > >
> > > > + trap_init();
> > > > notify_cpu_starting(curr_cpuid);
> > > > update_siblings_masks(curr_cpuid);
> > > > set_cpu_online(curr_cpuid, 1);
> > > > diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c
> > > > index ad14f4466d92..a390239818ae 100644
> > > > --- a/arch/riscv/kernel/traps.c
> > > > +++ b/arch/riscv/kernel/traps.c
> > > > @@ -174,7 +174,16 @@ int is_valid_bugaddr(unsigned long pc)
> > > > }
> > > > #endif /* CONFIG_GENERIC_BUG */
> > > >
> > > > -/* stvec & scratch is already set from head.S */
> > > > +/* stvec & scratch is already set from head.S when mmu is enabled */
> > > > void trap_init(void)
> > > > {
> > > > +#ifndef CONFIG_MMU
> > > > + /*
> > > > + * Set sup0 scratch register to 0, indicating to exception vector
> > > > + * that we are presently executing in the kernel
> > > > + */
> > > > + csr_write(CSR_SCRATCH, 0);
> > > > + /* Set the exception vector address */
> > > > + csr_write(CSR_TVEC, &handle_exception);
> > > > +#endif
> > > > }
> > > > --
> > > > 2.28.0
> > > >
> > >
> > > This issue seems to be only on the latest master branch of
> > > Linux stable tree so this fix need not be a stable fix.
> > >
> > > For MMU kernel, the CSR_TVEC is setup in relocate() function
> > > called from secondary_start_common() function of head.S
> > >
> > > For NoMMU kernel, we should set CSR_TVEC directly in
> > > secondary_start_common() function as "#else" case of the
> > > "#ifdef CONFIG_MMU".
> > >
> >
> > That would enable the trap only for secondary harts. But the exception
> > vector on boot hart
> > is still uninitialized. How about this change ?
> >
> > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
> > index d0c5c316e9bb..7822054dbd88 100644
> > --- a/arch/riscv/kernel/head.S
> > +++ b/arch/riscv/kernel/head.S
> > @@ -77,16 +77,6 @@ relocate:
> > csrw CSR_SATP, a0
> > .align 2
> > 1:
> > - /* Set trap vector to exception handler */
> > - la a0, handle_exception
> > - csrw CSR_TVEC, a0
> > -
> > - /*
> > - * Set sup0 scratch register to 0, indicating to exception vector that
> > - * we are presently executing in kernel.
> > - */
> > - csrw CSR_SCRATCH, zero
> > -
>
> Instead of having no trap vector setup here, we should
> at least have dummy trap vector (just like original code).
>
Ahh yes. We should include that.
> /* Set trap vector to spin forever to help debug */
> la a0, .Lsecondary_park
> csrw CSR_TVEC, a0
>
> > /* Reload the global pointer */
> > .option push
> > .option norelax
> > @@ -144,9 +134,23 @@ secondary_start_common:
> > la a0, swapper_pg_dir
> > call relocate
> > #endif
> > + call setup_trap_vector
> > tail smp_callin
> > #endif /* CONFIG_SMP */
> >
> > +.align 2
> > +setup_trap_vector:
> > + /* Set trap vector to exception handler */
> > + la a0, handle_exception
> > + csrw CSR_TVEC, a0
> > +
> > + /*
> > + * Set sup0 scratch register to 0, indicating to exception vector that
> > + * we are presently executing in kernel.
> > + */
> > + csrw CSR_SCRATCH, zero
> > + ret
> > +
> > .Lsecondary_park:
> > /* We lack SMP support or have too many harts, so park this hart */
> > wfi
> > @@ -240,6 +244,7 @@ clear_bss_done:
> > call relocate
> > #endif /* CONFIG_MMU */
> >
> > + call setup_trap_vector
> > /* Restore C environment */
> > la tp, init_task
> > sw zero, TASK_TI_CPU(tp)
>
> Apart from above, this looks good.
>
> Regards,
> Anup
--
Regards,
Atish
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-08-12 7:41 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-11 6:36 [PATCH] riscv: Setup exception vector for K210 properly Qiu Wenbo
2020-08-11 6:42 ` Damien Le Moal
2020-08-11 7:05 ` 邱文博
2020-08-11 7:44 ` Damien Le Moal
2020-08-11 6:43 ` Damien Le Moal
2020-08-11 8:40 ` Anup Patel
2020-08-11 18:45 ` Atish Patra
2020-08-12 1:09 ` Qiu Wenbo
2020-08-12 1:57 ` Anup Patel
2020-08-12 7:41 ` Atish Patra
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