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From: "Voon, Weifeng" <weifeng.voon@intel.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: "Ling, Pei Lee" <pei.lee.ling@intel.com>,
	Giuseppe Cavallaro <peppe.cavallaro@st.com>,
	Alexandre Torgue <alexandre.torgue@st.com>,
	"Jose Abreu" <joabreu@synopsys.com>,
	"David S . Miller" <davem@davemloft.net>,
	Jakub Kicinski <kuba@kernel.org>,
	Maxime Coquelin <mcoquelin.stm32@gmail.com>,
	Russell King <linux@armlinux.org.uk>,
	"Ong, Boon Leong" <boon.leong.ong@intel.com>,
	Wong Vee Khee <vee.khee.wong@linux.intel.com>,
	"Wong, Vee Khee" <vee.khee.wong@intel.com>,
	"Tan, Tee Min" <tee.min.tan@intel.com>,
	"Sit, Michael Wei Hong" <michael.wei.hong.sit@intel.com>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	"linux-stm32@st-md-mailman.stormreply.com" 
	<linux-stm32@st-md-mailman.stormreply.com>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH net-next V1 3/4] net: stmmac: Reconfigure the PHY WOL settings in stmmac_resume()
Date: Mon, 28 Jun 2021 07:48:49 +0000	[thread overview]
Message-ID: <CH0PR11MB53801A190BCEE45428039AC988039@CH0PR11MB5380.namprd11.prod.outlook.com> (raw)
In-Reply-To: <YNYF7XCyCIuwT0mT@lunn.ch>

> > I would like to rephase the commit message to make things clear:
> >
> > After PHY received a magic packet, the PHY WOL event will be
> > triggered. At the same time, the "Magic Packet Match Detected" bit is
> > set. In order for the PHY WOL event to be triggered again, the WOL
> > event status of "Magic Packet Match Detected" bit needs to be cleared.
> > When the PHY is in polling mode, the WOL event status needs to be
> > manually cleared.
> >
> > Ethtool settings will remain with WOL enabled after a S3/S4 suspend
> > resume cycle as expected. Hence, the driver should reconfigure the PHY
> > settings to reenable/disable WOL depending on the ethtool WOL settings
> > in the MAC resume flow.
> > The PHY set_wol flow would clear the WOL event status.
> 
> I would still argue that making use of a WoL interrupts and PHY polling is
> just wrong. But i assume you cannot fix this? You have a hardware design
> error?
> 
> The problem with this solution is you need to modify every MAC driver using
> the Marvell PHY. It does not scale.
> 
> Please try to find a solution within phylib or the marvell driver.
> Something which will work for any broken setup which is using WoL
> interrupts combined with polling.

Yes, I would not able to fix this as the PHY WOL event signal pin is connected
directly to the PMC. And, I do not have the info why the HW is designed in
this way. 

But, I totally agreed that this solution is not scalable. We will drop this
patch from this patchset for v2. We will find another solution and most
probably in phylib as this behavior most likely will be similar across all
other PHYs.

Weifeng

  reply	other threads:[~2021-06-28  7:48 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-21  9:45 [PATCH net-next V1 0/4] Add option to enable PHY WOL with PMT enabled Ling Pei Lee
2021-06-21  9:45 ` [PATCH net-next V1 1/4] net: stmmac: " Ling Pei Lee
2021-06-21  9:45 ` [PATCH net-next V1 2/4] stmmac: intel: Enable PHY WOL option in EHL Ling Pei Lee
2021-06-21  9:45 ` [PATCH net-next V1 3/4] net: stmmac: Reconfigure the PHY WOL settings in stmmac_resume() Ling Pei Lee
2021-06-21 13:05   ` Andrew Lunn
2021-06-23 10:06     ` Voon, Weifeng
2021-06-23 19:36       ` Andrew Lunn
2021-06-24 10:07         ` Voon, Weifeng
2021-06-24 13:40           ` Andrew Lunn
2021-06-25 15:58             ` Voon, Weifeng
2021-06-25 16:35               ` Andrew Lunn
2021-06-28  7:48                 ` Voon, Weifeng [this message]
2021-06-25 16:48               ` Russell King (Oracle)
2021-06-28  7:54                 ` Voon, Weifeng
2021-06-21  9:45 ` [PATCH net-next V1 4/4] stmmac: intel: set PCI_D3hot in suspend Ling Pei Lee

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