From: Jonathan McDowell <noodles@earth.li>
To: Russell King - ARM Linux admin <linux@armlinux.org.uk>,
Andrew Lunn <andrew@lunn.ch>,
Florian Fainelli <f.fainelli@gmail.com>,
Vladimir Oltean <olteanv@gmail.com>
Cc: Vivien Didelot <vivien.didelot@gmail.com>,
David Miller <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH net-next v5 2/3] net: dsa: qca8k: Improve SGMII interface handling
Date: Sat, 20 Jun 2020 11:31:05 +0100 [thread overview]
Message-ID: <a1916a08fc522ef774f1ceed7feadbcae5b305e9.1592648711.git.noodles@earth.li> (raw)
In-Reply-To: <cover.1592648711.git.noodles@earth.li>
This patch improves the handling of the SGMII interface on the QCA8K
devices. Previously the driver did no configuration of the port, even if
it was selected. We now configure it up in the appropriate
PHY/MAC/Base-X mode depending on what phylink tells us we are connected
to and ensure it is enabled.
Tested with a device where the CPU connection is RGMII (i.e. the common
current use case) + one where the CPU connection is SGMII. I don't have
any devices where the SGMII interface is brought out to something other
than the CPU.
Signed-off-by: Jonathan McDowell <noodles@earth.li>
---
drivers/net/dsa/qca8k.c | 33 ++++++++++++++++++++++++++++++++-
drivers/net/dsa/qca8k.h | 13 +++++++++++++
2 files changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 63b84789f16b..11d1c290d90f 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -673,6 +673,9 @@ qca8k_setup(struct dsa_switch *ds)
/* Flush the FDB table */
qca8k_fdb_flush(priv);
+ /* We don't have interrupts for link changes, so we need to poll */
+ ds->pcs_poll = true;
+
return 0;
}
@@ -681,7 +684,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
const struct phylink_link_state *state)
{
struct qca8k_priv *priv = ds->priv;
- u32 reg;
+ u32 reg, val;
switch (port) {
case 0: /* 1st CPU port */
@@ -740,6 +743,34 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
case PHY_INTERFACE_MODE_1000BASEX:
/* Enable SGMII on the port */
qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
+
+ /* Enable/disable SerDes auto-negotiation as necessary */
+ val = qca8k_read(priv, QCA8K_REG_PWS);
+ if (phylink_autoneg_inband(mode))
+ val &= ~QCA8K_PWS_SERDES_AEN_DIS;
+ else
+ val |= QCA8K_PWS_SERDES_AEN_DIS;
+ qca8k_write(priv, QCA8K_REG_PWS, val);
+
+ /* Configure the SGMII parameters */
+ val = qca8k_read(priv, QCA8K_REG_SGMII_CTRL);
+
+ val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
+ QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
+
+ if (dsa_is_cpu_port(ds, port)) {
+ /* CPU port, we're talking to the CPU MAC, be a PHY */
+ val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
+ val |= QCA8K_SGMII_MODE_CTRL_PHY;
+ } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
+ val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
+ val |= QCA8K_SGMII_MODE_CTRL_MAC;
+ } else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
+ val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
+ val |= QCA8K_SGMII_MODE_CTRL_BASEX;
+ }
+
+ qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
break;
default:
dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index 42d6ea24eb14..10ef2bca2cde 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -36,6 +36,8 @@
#define QCA8K_MAX_DELAY 3
#define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
#define QCA8K_PORT_PAD_SGMII_EN BIT(7)
+#define QCA8K_REG_PWS 0x010
+#define QCA8K_PWS_SERDES_AEN_DIS BIT(7)
#define QCA8K_REG_MODULE_EN 0x030
#define QCA8K_MODULE_EN_MIB BIT(0)
#define QCA8K_REG_MIB 0x034
@@ -69,6 +71,7 @@
#define QCA8K_PORT_STATUS_LINK_UP BIT(8)
#define QCA8K_PORT_STATUS_LINK_AUTO BIT(9)
#define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10)
+#define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12)
#define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
#define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
#define QCA8K_PORT_HDR_CTRL_RX_S 2
@@ -77,6 +80,16 @@
#define QCA8K_PORT_HDR_CTRL_ALL 2
#define QCA8K_PORT_HDR_CTRL_MGMT 1
#define QCA8K_PORT_HDR_CTRL_NONE 0
+#define QCA8K_REG_SGMII_CTRL 0x0e0
+#define QCA8K_SGMII_EN_PLL BIT(1)
+#define QCA8K_SGMII_EN_RX BIT(2)
+#define QCA8K_SGMII_EN_TX BIT(3)
+#define QCA8K_SGMII_EN_SD BIT(4)
+#define QCA8K_SGMII_CLK125M_DELAY BIT(7)
+#define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23))
+#define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22)
+#define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22)
+#define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22)
/* EEE control registers */
#define QCA8K_REG_EEE_CTRL 0x100
--
2.20.1
next prev parent reply other threads:[~2020-06-20 10:32 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-05 18:08 [PATCH 0/2] net: dsa: qca8k: Add SGMII configuration options Jonathan McDowell
2020-06-05 18:10 ` [PATCH 1/2] dt-bindings: net: dsa: qca8k: document SGMII properties Jonathan McDowell
2020-06-15 17:45 ` Rob Herring
2020-06-15 18:15 ` Jonathan McDowell
2020-06-05 18:10 ` [PATCH 2/2] net: dsa: qca8k: introduce SGMII configuration options Jonathan McDowell
2020-06-05 18:28 ` Marek Behun
2020-06-05 18:38 ` Andrew Lunn
2020-06-06 7:49 ` Jonathan McDowell
2020-06-06 8:37 ` Russell King - ARM Linux admin
2020-06-06 10:59 ` Jonathan McDowell
2020-06-06 13:43 ` Russell King - ARM Linux admin
2020-06-06 18:02 ` Jonathan McDowell
2020-06-06 14:03 ` Andrew Lunn
2020-06-08 18:39 ` [RFC PATCH v2] net: dsa: qca8k: Improve SGMII interface handling Jonathan McDowell
2020-06-08 19:10 ` Russell King - ARM Linux admin
2020-06-10 19:13 ` [RFC PATCH v3 0/2] " Jonathan McDowell
2020-06-10 19:14 ` [PATCH 1/2] net: dsa: qca8k: Switch to PHYLINK instead of PHYLIB Jonathan McDowell
2020-06-11 3:15 ` Florian Fainelli
2020-06-11 8:55 ` Russell King - ARM Linux admin
2020-06-11 9:01 ` Vladimir Oltean
2020-06-12 11:53 ` Jonathan McDowell
2020-06-11 8:58 ` Vladimir Oltean
2020-06-11 11:04 ` Jonathan McDowell
2020-06-10 19:15 ` [PATCH 2/2] net: dsa: qca8k: Improve SGMII interface handling Jonathan McDowell
2020-06-11 3:31 ` Florian Fainelli
2020-06-11 17:47 ` Jonathan McDowell
2020-06-11 8:58 ` Russell King - ARM Linux admin
2020-06-10 23:29 ` [RFC PATCH v3 0/2] " David Miller
2020-06-13 11:31 ` [RFC PATCH v4 " Jonathan McDowell
2020-06-13 11:31 ` [RFC PATCH v4 1/2] net: dsa: qca8k: Switch to PHYLINK instead of PHYLIB Jonathan McDowell
2020-06-13 19:30 ` Vladimir Oltean
2020-06-13 11:32 ` [RFC PATCH v4 2/2] net: dsa: qca8k: Improve SGMII interface handling Jonathan McDowell
2020-06-13 20:10 ` Vladimir Oltean
2020-06-14 17:20 ` Jonathan McDowell
2020-06-20 10:30 ` [PATCH net-next v5 0/3] " Jonathan McDowell
2020-06-20 10:30 ` [PATCH net-next v5 1/3] net: dsa: qca8k: Switch to PHYLINK instead of PHYLIB Jonathan McDowell
2020-06-20 10:31 ` Jonathan McDowell [this message]
2020-06-20 10:31 ` [PATCH net-next v5 3/3] net: dsa: qca8k: Minor comment spelling fix Jonathan McDowell
2020-06-22 22:54 ` [PATCH net-next v5 0/3] net: dsa: qca8k: Improve SGMII interface handling David Miller
2020-06-19 8:12 ` [PATCH 2/2] net: dsa: qca8k: introduce SGMII configuration options Dan Carpenter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=a1916a08fc522ef774f1ceed7feadbcae5b305e9.1592648711.git.noodles@earth.li \
--to=noodles@earth.li \
--cc=andrew@lunn.ch \
--cc=davem@davemloft.net \
--cc=f.fainelli@gmail.com \
--cc=kuba@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux@armlinux.org.uk \
--cc=netdev@vger.kernel.org \
--cc=olteanv@gmail.com \
--cc=vivien.didelot@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).