From: Thomas Gleixner <tglx@linutronix.de>
To: "Liang, Kan" <kan.liang@linux.intel.com>
Cc: peterz@infradead.org, acme@kernel.org, mingo@redhat.com,
linux-kernel@vger.kernel.org, jolsa@kernel.org,
eranian@google.com, alexander.shishkin@linux.intel.com,
ak@linux.intel.com
Subject: Re: [PATCH V3 01/23] perf/x86: Support outputting XMM registers
Date: Tue, 26 Mar 2019 14:47:41 +0100 (CET) [thread overview]
Message-ID: <alpine.DEB.2.21.1903261442470.1789@nanos.tec.linutronix.de> (raw)
In-Reply-To: <5533614f-3d97-6e50-c63c-bee33c00c93b@linux.intel.com>
On Tue, 26 Mar 2019, Liang, Kan wrote:
> On 3/25/2019 8:11 PM, Thomas Gleixner wrote:
>
> -#define REG_RESERVED (~((1ULL << PERF_REG_X86_MAX) - 1ULL))
> +#define REG_RESERVED 0
What's the point of having this around?
> int perf_reg_validate(u64 mask)
> {
> if (!mask || mask & REG_RESERVED)
> return -EINVAL;
mask & 0 == 0, right? So which bits are you checking here?
Thanks,
tglx
next prev parent reply other threads:[~2019-03-26 13:47 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-22 16:36 [PATCH V3 00/23] perf: Add Icelake support kan.liang
2019-03-22 16:36 ` [PATCH V3 01/23] perf/x86: Support outputting XMM registers kan.liang
2019-03-22 17:08 ` Peter Zijlstra
2019-03-22 17:22 ` Andi Kleen
2019-03-23 9:56 ` Peter Zijlstra
2019-03-25 20:35 ` Liang, Kan
2019-03-26 0:02 ` Thomas Gleixner
2019-03-26 0:11 ` Thomas Gleixner
2019-03-26 13:14 ` Liang, Kan
2019-03-26 13:47 ` Thomas Gleixner [this message]
2019-03-26 13:55 ` Liang, Kan
2019-03-22 16:36 ` [PATCH V3 02/23] perf/x86/intel: Extract memory code PEBS parser for reuse kan.liang
2019-03-22 16:36 ` [PATCH V3 03/23] perf/x86/intel/ds: Extract code of event update in short period kan.liang
2019-03-22 16:36 ` [PATCH V3 04/23] perf/x86/intel: Support adaptive PEBSv4 kan.liang
2019-03-22 16:37 ` [PATCH V3 05/23] perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them kan.liang
2019-03-22 16:37 ` [PATCH V3 06/23] perf/x86: Support constraint ranges kan.liang
2019-03-22 16:37 ` [PATCH V3 07/23] perf/x86/intel: Add Icelake support kan.liang
2019-03-22 16:37 ` [PATCH V3 08/23] perf/x86/intel/cstate: " kan.liang
2019-03-22 16:37 ` [PATCH V3 09/23] perf/x86/intel/rapl: " kan.liang
2019-03-22 16:37 ` [PATCH V3 10/23] perf/x86/msr: " kan.liang
2019-03-22 16:37 ` [PATCH V3 11/23] perf/x86/intel/uncore: Add Intel Icelake uncore support kan.liang
2019-03-22 16:37 ` [PATCH V3 12/23] perf/core: Support a REMOVE transaction kan.liang
2019-03-22 16:37 ` [PATCH V3 13/23] perf/x86/intel: Basic support for metrics counters kan.liang
2019-03-22 16:37 ` [PATCH V3 14/23] perf/x86/intel: Support overflows on SLOTS kan.liang
2019-03-22 16:37 ` [PATCH V3 15/23] perf/x86/intel: Support hardware TopDown metrics kan.liang
2019-03-22 16:37 ` [PATCH V3 16/23] perf/x86/intel: Set correct weight for topdown subevent counters kan.liang
2019-03-22 16:37 ` [PATCH V3 17/23] perf/x86/intel: Export new top down events for Icelake kan.liang
2019-03-22 16:37 ` [PATCH V3 18/23] perf/x86/intel: Disable sampling read slots and topdown kan.liang
2019-03-22 16:37 ` [PATCH V3 19/23] perf/x86/intel: Support CPUID 10.ECX to disable fixed counters kan.liang
2019-03-22 16:37 ` [PATCH V3 20/23] perf, tools: Add support for recording and printing XMM registers kan.liang
2019-03-22 16:37 ` [PATCH 21/23] perf, tools, stat: Support new per thread TopDown metrics kan.liang
2019-03-22 16:37 ` [PATCH V3 22/23] perf, tools: Add documentation for topdown metrics kan.liang
2019-03-22 16:37 ` [PATCH V3 23/23] perf vendor events intel: Add JSON files for Icelake kan.liang
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