Re: [linux-sunxi] [PATCH 1/4] phy: sun4i-usb: support PHY0 on H3 in MUSB mode

Re: [linux-sunxi] [PATCH 1/4] phy: sun4i-usb: support PHY0 on H3 in MUSB mode

[Ondřej Jirman]

Dne 16.1.2017 v 20:14 Icenowy Zheng napsal(a):
> The PHY0 on H3 can be wired either to MUSB controller or OHCI/EHCI
> controller.
> 
> The original driver wired it to OHCI/EHCI controller; however, as the
> code to use PHY0 as OHCI/EHCI is missing, it makes the PHY fully
> unusable.
> 
> Rename the register (according to its function and the name in BSP
> driver), and remove the code which wires the PHY0 to OHCI/EHCI, as MUSB
> can support both peripheral and host mode (although the host mode of
> MUSB is buggy).
> 
> The register that is renamed is now unused, as its initial value is just
> MUSB mode. However, when OHCI/EHCI mode support is added, the register
> can be used again.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
>  drivers/phy/phy-sun4i-usb.c | 25 +++++++++----------------
>  1 file changed, 9 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
> index bf28a0fdd569..6b193a635c6b 100644
> --- a/drivers/phy/phy-sun4i-usb.c
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -49,7 +49,7 @@
>  #define REG_PHYBIST			0x08
>  #define REG_PHYTUNE			0x0c
>  #define REG_PHYCTL_A33			0x10
> -#define REG_PHY_UNK_H3			0x20
> +#define REG_PHY_OTGCTL			0x20

You have added REG_PHY_OTGCTL, but it is not used below.

regards,
  o.

>  #define REG_PMU_UNK1			0x10
>  
> @@ -269,23 +269,16 @@ static int sun4i_usb_phy_init(struct phy *_phy)
>  		writel(val & ~2, phy->pmu + REG_PMU_UNK1);
>  	}
>  
> -	if (data->cfg->type == sun8i_h3_phy) {
> -		if (phy->index == 0) {
> -			val = readl(data->base + REG_PHY_UNK_H3);
> -			writel(val & ~1, data->base + REG_PHY_UNK_H3);
> -		}
> -	} else {
> -		/* Enable USB 45 Ohm resistor calibration */
> -		if (phy->index == 0)
> -			sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
> +	/* Enable USB 45 Ohm resistor calibration */
> +	if (phy->index == 0)
> +		sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
>  
> -		/* Adjust PHY's magnitude and rate */
> -		sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
> +	/* Adjust PHY's magnitude and rate */
> +	sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
>  
> -		/* Disconnect threshold adjustment */
> -		sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
> -				    data->cfg->disc_thresh, 2);
> -	}
> +	/* Disconnect threshold adjustment */
> +	sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
> +			    data->cfg->disc_thresh, 2);
>  
>  	sun4i_usb_phy_passby(phy, 1);
>  
> 

Re: [PATCH 1/4] phy: sun4i-usb: support PHY0 on H3 in MUSB mode

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 713 bytes --]

On Tue, Jan 17, 2017 at 03:14:46AM +0800, Icenowy Zheng wrote:
> The PHY0 on H3 can be wired either to MUSB controller or OHCI/EHCI
> controller.
> 
> The original driver wired it to OHCI/EHCI controller; however, as the
> code to use PHY0 as OHCI/EHCI is missing, it makes the PHY fully
> unusable.
> 
> Rename the register (according to its function and the name in BSP
> driver), and remove the code which wires the PHY0 to OHCI/EHCI, as MUSB
> can support both peripheral and host mode (although the host mode of
> MUSB is buggy).

Can you elaborate on that? What's wrong with it?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]

Re: [PATCH 1/4] phy: sun4i-usb: support PHY0 on H3 in MUSB mode

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1460 bytes --]

On Wed, Jan 18, 2017 at 12:57:08AM +0800, Icenowy Zheng wrote:
> 
> 
> 17.01.2017, 16:06, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> > On Tue, Jan 17, 2017 at 03:14:46AM +0800, Icenowy Zheng wrote:
> >>  The PHY0 on H3 can be wired either to MUSB controller or OHCI/EHCI
> >>  controller.
> >>
> >>  The original driver wired it to OHCI/EHCI controller; however, as the
> >>  code to use PHY0 as OHCI/EHCI is missing, it makes the PHY fully
> >>  unusable.
> >>
> >>  Rename the register (according to its function and the name in BSP
> >>  driver), and remove the code which wires the PHY0 to OHCI/EHCI, as MUSB
> >>  can support both peripheral and host mode (although the host mode of
> >>  MUSB is buggy).
> >
> > Can you elaborate on that? What's wrong with it?
> 
> The configuration is at bit 0 of register 0x20 in PHY.
> 
> When the PHY is reseted, it defaults as MUSB mode.
> 
> However, the original author of the H3 PHY code seems to be lack of
> this knowledge (He named it PHY_UNK_H3), and changed the PHY to HCI
> mode.
> 
> I just removed the code that wires it to HCI mode, thus it will work
> in MUSB mode, with my sun8i-h3-musb patch.

I have no idea what you mean by MUSB mode.

Do you mean that the previous code was only working in host mode, and
now it only works in peripheral?

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]

Re: [PATCH 1/4] phy: sun4i-usb: support PHY0 on H3 in MUSB mode

[Chen-Yu Tsai]

Hi,

On Wed, Jan 18, 2017 at 4:06 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Wed, Jan 18, 2017 at 12:57:08AM +0800, Icenowy Zheng wrote:
>>
>>
>> 17.01.2017, 16:06, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
>> > On Tue, Jan 17, 2017 at 03:14:46AM +0800, Icenowy Zheng wrote:
>> >>  The PHY0 on H3 can be wired either to MUSB controller or OHCI/EHCI
>> >>  controller.
>> >>
>> >>  The original driver wired it to OHCI/EHCI controller; however, as the
>> >>  code to use PHY0 as OHCI/EHCI is missing, it makes the PHY fully
>> >>  unusable.
>> >>
>> >>  Rename the register (according to its function and the name in BSP
>> >>  driver), and remove the code which wires the PHY0 to OHCI/EHCI, as MUSB
>> >>  can support both peripheral and host mode (although the host mode of
>> >>  MUSB is buggy).
>> >
>> > Can you elaborate on that? What's wrong with it?
>>
>> The configuration is at bit 0 of register 0x20 in PHY.
>>
>> When the PHY is reseted, it defaults as MUSB mode.
>>
>> However, the original author of the H3 PHY code seems to be lack of
>> this knowledge (He named it PHY_UNK_H3), and changed the PHY to HCI
>> mode.
>>
>> I just removed the code that wires it to HCI mode, thus it will work
>> in MUSB mode, with my sun8i-h3-musb patch.
>
> I have no idea what you mean by MUSB mode.
>
> Do you mean that the previous code was only working in host mode, and
> now it only works in peripheral?

>From what I understand, with the H3, Allwinner has put a mux
in front of the MUSB controller. The mux can send the USB data
to/from the MUSB controller, or a standard EHCI/OHCI pair.
This register controls said mux.

This means we can use a proper USB host for host mode,
instead of the limited support in MUSB.

ChenYu

>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com

Re: [PATCH 1/4] phy: sun4i-usb: support PHY0 on H3 in MUSB mode

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 2123 bytes --]

On Wed, Jan 18, 2017 at 04:09:32AM +0800, Chen-Yu Tsai wrote:
> Hi,
> 
> On Wed, Jan 18, 2017 at 4:06 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > On Wed, Jan 18, 2017 at 12:57:08AM +0800, Icenowy Zheng wrote:
> >>
> >>
> >> 17.01.2017, 16:06, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> >> > On Tue, Jan 17, 2017 at 03:14:46AM +0800, Icenowy Zheng wrote:
> >> >>  The PHY0 on H3 can be wired either to MUSB controller or OHCI/EHCI
> >> >>  controller.
> >> >>
> >> >>  The original driver wired it to OHCI/EHCI controller; however, as the
> >> >>  code to use PHY0 as OHCI/EHCI is missing, it makes the PHY fully
> >> >>  unusable.
> >> >>
> >> >>  Rename the register (according to its function and the name in BSP
> >> >>  driver), and remove the code which wires the PHY0 to OHCI/EHCI, as MUSB
> >> >>  can support both peripheral and host mode (although the host mode of
> >> >>  MUSB is buggy).
> >> >
> >> > Can you elaborate on that? What's wrong with it?
> >>
> >> The configuration is at bit 0 of register 0x20 in PHY.
> >>
> >> When the PHY is reseted, it defaults as MUSB mode.
> >>
> >> However, the original author of the H3 PHY code seems to be lack of
> >> this knowledge (He named it PHY_UNK_H3), and changed the PHY to HCI
> >> mode.
> >>
> >> I just removed the code that wires it to HCI mode, thus it will work
> >> in MUSB mode, with my sun8i-h3-musb patch.
> >
> > I have no idea what you mean by MUSB mode.
> >
> > Do you mean that the previous code was only working in host mode, and
> > now it only works in peripheral?
> 
> From what I understand, with the H3, Allwinner has put a mux
> in front of the MUSB controller. The mux can send the USB data
> to/from the MUSB controller, or a standard EHCI/OHCI pair.
> This register controls said mux.
> 
> This means we can use a proper USB host for host mode,
> instead of the limited support in MUSB.

But musb can still operate as a host, right?

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]

Re: [linux-sunxi] Re: [PATCH 1/4] phy: sun4i-usb: support PHY0 on H3 in MUSB mode

[Karsten Merker]

On Thu, Jan 19, 2017 at 11:10:08PM +0800, Icenowy Zheng wrote:
> 19.01.2017, 22:34, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> > On Wed, Jan 18, 2017 at 04:09:32AM +0800, Chen-Yu Tsai wrote:
> >>  On Wed, Jan 18, 2017 at 4:06 AM, Maxime Ripard
> >>  <maxime.ripard@free-electrons.com> wrote:
> >>  > On Wed, Jan 18, 2017 at 12:57:08AM +0800, Icenowy Zheng wrote:
> >>  >> 17.01.2017, 16:06, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
> >>  >> > On Tue, Jan 17, 2017 at 03:14:46AM +0800, Icenowy Zheng wrote:
> >>  >> >> The PHY0 on H3 can be wired either to MUSB controller or OHCI/EHCI
> >>  >> >> controller.
> >>  >> >>
> >>  >> >> The original driver wired it to OHCI/EHCI controller; however, as the
> >>  >> >> code to use PHY0 as OHCI/EHCI is missing, it makes the PHY fully
> >>  >> >> unusable.
> >>  >> >>
> >>  >> >> Rename the register (according to its function and the name in BSP
> >>  >> >> driver), and remove the code which wires the PHY0 to OHCI/EHCI, as MUSB
> >>  >> >> can support both peripheral and host mode (although the host mode of
> >>  >> >> MUSB is buggy).
> >>  >> >
> >>  >> > Can you elaborate on that? What's wrong with it?
> >>  >>
> >>  >> The configuration is at bit 0 of register 0x20 in PHY.
> >>  >>
> >>  >> When the PHY is reseted, it defaults as MUSB mode.
> >>  >>
> >>  >> However, the original author of the H3 PHY code seems to be lack of
> >>  >> this knowledge (He named it PHY_UNK_H3), and changed the PHY to HCI
> >>  >> mode.
> >>  >>
> >>  >> I just removed the code that wires it to HCI mode, thus it will work
> >>  >> in MUSB mode, with my sun8i-h3-musb patch.
> >>  >
> >>  > I have no idea what you mean by MUSB mode.
> >>  >
> >>  > Do you mean that the previous code was only working in host mode, and
> >>  > now it only works in peripheral?
> >>
> >>  From what I understand, with the H3, Allwinner has put a mux
> >>  in front of the MUSB controller. The mux can send the USB data
> >>  to/from the MUSB controller, or a standard EHCI/OHCI pair.
> >>  This register controls said mux.
> >>
> >>  This means we can use a proper USB host for host mode,
> >>  instead of the limited support in MUSB.
> >
> > But musb can still operate as a host, right?
> 
> Yes!

Hello,

I don't know how the MUSB implementation in the H3 behaves as I
don't have any H3-based systems, but if it should happen to be
similar to the one in the A31s, it probably isn't a full-fledged
alternative to using an OHCI/EHCI controller.

>From my practical experiments with the MUSB in the A31s in host
mode I can report that I hadn't been able to get multiple HIDs
(in my case keyboard and mouse) working at the same time.  The
keyboard alone worked without problems, the mouse alone worked
without problems, but when both were connected, only one of them
worked.

I had at that time talked to Hans de Goede about the problem and
if I remenber correctly, he had mentioned that the MUSB has
problems servicing more than one device that does interrupt
transfers (as HIDs do).

Hans, can you perhaps shed some light on this?

Regards,
Karsten
-- 
Gem. Par. 28 Abs. 4 Bundesdatenschutzgesetz widerspreche ich der Nutzung
sowie der Weitergabe meiner personenbezogenen Daten für Zwecke der
Werbung sowie der Markt- oder Meinungsforschung.

Re: [linux-sunxi] Re: [PATCH 1/4] phy: sun4i-usb: support PHY0 on H3 in MUSB mode

[Hans de Goede]

HI,

On 19-01-17 21:27, Karsten Merker wrote:
> On Thu, Jan 19, 2017 at 11:10:08PM +0800, Icenowy Zheng wrote:
>> 19.01.2017, 22:34, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
>>> On Wed, Jan 18, 2017 at 04:09:32AM +0800, Chen-Yu Tsai wrote:
>>>>  On Wed, Jan 18, 2017 at 4:06 AM, Maxime Ripard
>>>>  <maxime.ripard@free-electrons.com> wrote:
>>>>  > On Wed, Jan 18, 2017 at 12:57:08AM +0800, Icenowy Zheng wrote:
>>>>  >> 17.01.2017, 16:06, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
>>>>  >> > On Tue, Jan 17, 2017 at 03:14:46AM +0800, Icenowy Zheng wrote:
>>>>  >> >> The PHY0 on H3 can be wired either to MUSB controller or OHCI/EHCI
>>>>  >> >> controller.
>>>>  >> >>
>>>>  >> >> The original driver wired it to OHCI/EHCI controller; however, as the
>>>>  >> >> code to use PHY0 as OHCI/EHCI is missing, it makes the PHY fully
>>>>  >> >> unusable.
>>>>  >> >>
>>>>  >> >> Rename the register (according to its function and the name in BSP
>>>>  >> >> driver), and remove the code which wires the PHY0 to OHCI/EHCI, as MUSB
>>>>  >> >> can support both peripheral and host mode (although the host mode of
>>>>  >> >> MUSB is buggy).
>>>>  >> >
>>>>  >> > Can you elaborate on that? What's wrong with it?
>>>>  >>
>>>>  >> The configuration is at bit 0 of register 0x20 in PHY.
>>>>  >>
>>>>  >> When the PHY is reseted, it defaults as MUSB mode.
>>>>  >>
>>>>  >> However, the original author of the H3 PHY code seems to be lack of
>>>>  >> this knowledge (He named it PHY_UNK_H3), and changed the PHY to HCI
>>>>  >> mode.
>>>>  >>
>>>>  >> I just removed the code that wires it to HCI mode, thus it will work
>>>>  >> in MUSB mode, with my sun8i-h3-musb patch.
>>>>  >
>>>>  > I have no idea what you mean by MUSB mode.
>>>>  >
>>>>  > Do you mean that the previous code was only working in host mode, and
>>>>  > now it only works in peripheral?
>>>>
>>>>  From what I understand, with the H3, Allwinner has put a mux
>>>>  in front of the MUSB controller. The mux can send the USB data
>>>>  to/from the MUSB controller, or a standard EHCI/OHCI pair.
>>>>  This register controls said mux.
>>>>
>>>>  This means we can use a proper USB host for host mode,
>>>>  instead of the limited support in MUSB.
>>>
>>> But musb can still operate as a host, right?
>>
>> Yes!
>
> Hello,
>
> I don't know how the MUSB implementation in the H3 behaves as I
> don't have any H3-based systems, but if it should happen to be
> similar to the one in the A31s, it probably isn't a full-fledged
> alternative to using an OHCI/EHCI controller.

You right it isn't which is why I suggested that the phy-sun4i-usb
code should set the mux to the OCHI/EHCI pair when the id pin
is pulled low (host-mode).

> From my practical experiments with the MUSB in the A31s in host
> mode I can report that I hadn't been able to get multiple HIDs
> (in my case keyboard and mouse) working at the same time.  The
> keyboard alone worked without problems, the mouse alone worked
> without problems, but when both were connected, only one of them
> worked.
>
> I had at that time talked to Hans de Goede about the problem and
> if I remenber correctly, he had mentioned that the MUSB has
> problems servicing more than one device that does interrupt
> transfers (as HIDs do).
>
> Hans, can you perhaps shed some light on this?

Everything you've said is correct, the MUSB can emulate a
host-controller, but it is not really one and when possible
should not be used as such.

Regards,

Hans

Re: [linux-sunxi] Re: [PATCH 1/4] phy: sun4i-usb: support PHY0 on H3 in MUSB mode

[Hans de Goede]

HI,

On 22-01-17 10:39, Icenowy Zheng wrote:
>
>
> 20.01.2017, 16:04, "Hans de Goede" <hdegoede@redhat.com>:
>> HI,
>>
>> On 19-01-17 21:27, Karsten Merker wrote:
>>>  On Thu, Jan 19, 2017 at 11:10:08PM +0800, Icenowy Zheng wrote:
>>>>  19.01.2017, 22:34, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
>>>>>  On Wed, Jan 18, 2017 at 04:09:32AM +0800, Chen-Yu Tsai wrote:
>>>>>>   On Wed, Jan 18, 2017 at 4:06 AM, Maxime Ripard
>>>>>>   <maxime.ripard@free-electrons.com> wrote:
>>>>>>   > On Wed, Jan 18, 2017 at 12:57:08AM +0800, Icenowy Zheng wrote:
>>>>>>   >> 17.01.2017, 16:06, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
>>>>>>   >> > On Tue, Jan 17, 2017 at 03:14:46AM +0800, Icenowy Zheng wrote:
>>>>>>   >> >> The PHY0 on H3 can be wired either to MUSB controller or OHCI/EHCI
>>>>>>   >> >> controller.
>>>>>>   >> >>
>>>>>>   >> >> The original driver wired it to OHCI/EHCI controller; however, as the
>>>>>>   >> >> code to use PHY0 as OHCI/EHCI is missing, it makes the PHY fully
>>>>>>   >> >> unusable.
>>>>>>   >> >>
>>>>>>   >> >> Rename the register (according to its function and the name in BSP
>>>>>>   >> >> driver), and remove the code which wires the PHY0 to OHCI/EHCI, as MUSB
>>>>>>   >> >> can support both peripheral and host mode (although the host mode of
>>>>>>   >> >> MUSB is buggy).
>>>>>>   >> >
>>>>>>   >> > Can you elaborate on that? What's wrong with it?
>>>>>>   >>
>>>>>>   >> The configuration is at bit 0 of register 0x20 in PHY.
>>>>>>   >>
>>>>>>   >> When the PHY is reseted, it defaults as MUSB mode.
>>>>>>   >>
>>>>>>   >> However, the original author of the H3 PHY code seems to be lack of
>>>>>>   >> this knowledge (He named it PHY_UNK_H3), and changed the PHY to HCI
>>>>>>   >> mode.
>>>>>>   >>
>>>>>>   >> I just removed the code that wires it to HCI mode, thus it will work
>>>>>>   >> in MUSB mode, with my sun8i-h3-musb patch.
>>>>>>   >
>>>>>>   > I have no idea what you mean by MUSB mode.
>>>>>>   >
>>>>>>   > Do you mean that the previous code was only working in host mode, and
>>>>>>   > now it only works in peripheral?
>>>>>>
>>>>>>   From what I understand, with the H3, Allwinner has put a mux
>>>>>>   in front of the MUSB controller. The mux can send the USB data
>>>>>>   to/from the MUSB controller, or a standard EHCI/OHCI pair.
>>>>>>   This register controls said mux.
>>>>>>
>>>>>>   This means we can use a proper USB host for host mode,
>>>>>>   instead of the limited support in MUSB.
>>>>>
>>>>>  But musb can still operate as a host, right?
>>>>
>>>>  Yes!
>>>
>>>  Hello,
>>>
>>>  I don't know how the MUSB implementation in the H3 behaves as I
>>>  don't have any H3-based systems, but if it should happen to be
>>>  similar to the one in the A31s, it probably isn't a full-fledged
>>>  alternative to using an OHCI/EHCI controller.
>>
>> You right it isn't which is why I suggested that the phy-sun4i-usb
>> code should set the mux to the OCHI/EHCI pair when the id pin
>> is pulled low (host-mode).
>>
>>>  From my practical experiments with the MUSB in the A31s in host
>>>  mode I can report that I hadn't been able to get multiple HIDs
>>>  (in my case keyboard and mouse) working at the same time. The
>>>  keyboard alone worked without problems, the mouse alone worked
>>>  without problems, but when both were connected, only one of them
>>>  worked.
>>>
>>>  I had at that time talked to Hans de Goede about the problem and
>>>  if I remenber correctly, he had mentioned that the MUSB has
>>>  problems servicing more than one device that does interrupt
>>>  transfers (as HIDs do).
>>>
>>>  Hans, can you perhaps shed some light on this?
>>
>> Everything you've said is correct, the MUSB can emulate a
>> host-controller, but it is not really one and when possible
>> should not be used as such.
>
> But implement proper EHCI/OHCI pair and MUSB coexistence needs
> a lot of code

No it doesn't see the previous thread on this I give an example
of how this can be implemented there, and it is not a lot of
work, it just requires someone to do it.

> and MUSB can still work.
>
> We can now just enable MUSB, then after the coexistence is done,
> switch to use MUSB for peripheral and {E,O}HCI for host.

I'm not in favor of these kinda hacks, we are creating expectations
of how things work then only to change them later with a possible
risk of regression things for some users / use-cases. Lets do
this the right way in one go please.

> Seems that SoCs after sun8iw7 (H3) all have this feature. (At least
> I verified it on H3, V3s, A64, H5)
>
> P.S. The implementation on FreeBSD of A64 PHY uses a dedicated
> PHY number for the HCI pair, which seems to break the DT compatibility
> between Linux and FreeBSD.

That is unfortunate and also weird since AFAICT there is only
one phy and it is the phy data lines which get muxed not the
physical phy. Anyways can you contact them and ask them to
please not do that ?

Regards,

Hans