From: John Garry <john.garry@huawei.com>
To: Marc Zyngier <maz@kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: chenxiang <chenxiang66@hisilicon.com>,
Zhou Wang <wangzhou1@hisilicon.com>,
Ming Lei <ming.lei@redhat.com>,
Jason Cooper <jason@lakedaemon.net>,
Thomas Gleixner <tglx@linutronix.de>,
"luojiaxing@huawei.com" <luojiaxing@huawei.com>
Subject: Re: [PATCH v3 2/2] irqchip/gic-v3-its: Balance initial LPI affinity across CPUs
Date: Wed, 18 Mar 2020 12:22:09 +0000 [thread overview]
Message-ID: <d3a6435b-bc1f-e518-6461-2ebff72bbc59@huawei.com> (raw)
In-Reply-To: <20200316115433.9017-3-maz@kernel.org>
I may have an idea about this:
irq 196, cpu list 0-31, effective list 82
Just going back to comment on the code:
> +/*
> + * As suggested by Thomas Gleixner in:
> + * https://lore.kernel.org/r/87h80q2aoc.fsf@nanos.tec.linutronix.de
> + */
> +static int its_select_cpu(struct irq_data *d,
> + const struct cpumask *aff_mask)
> +{
> + struct its_device *its_dev = irq_data_get_irq_chip_data(d);
> + cpumask_var_t tmpmask;
> + int cpu, node;
> +
> + if (!alloc_cpumask_var(&tmpmask, GFP_KERNEL))
> + return -ENOMEM;
> +
> + node = its_dev->its->numa_node;
> +
> + if (!irqd_affinity_is_managed(d)) {
> + /* First try the NUMA node */
> + if (node != NUMA_NO_NODE) {
> + /*
> + * Try the intersection of the affinity mask and the
> + * node mask (and the online mask, just to be safe).
> + */
> + cpumask_and(tmpmask, cpumask_of_node(node), aff_mask);
> + cpumask_and(tmpmask, tmpmask, cpu_online_mask);
> +
> + /* If that doesn't work, try the nodemask itself */
So if tmpmsk is empty...
> + if (cpumask_empty(tmpmask))
> + cpumask_and(tmpmask, cpumask_of_node(node), cpu_online_mask);
now the tmpmask may have no intersection with the aff_mask...
> +
> + cpu = cpumask_pick_least_loaded(d, tmpmask);
> + if (cpu < nr_cpu_ids)
> + goto out;
> +
> + /* If we can't cross sockets, give up */
> + if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144))
> + goto out;
> +
> + /* If the above failed, expand the search */
> + }
SNIP
> +out:
> + free_cpumask_var(tmpmask);
> +
> + pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu);
> + return cpu;
> +}
> +
> static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
> bool force)
> {
> - unsigned int cpu;
> - const struct cpumask *cpu_mask = cpu_online_mask;
> struct its_device *its_dev = irq_data_get_irq_chip_data(d);
> struct its_collection *target_col;
> u32 id = its_get_event_id(d);
> + int cpu;
>
> /* A forwarded interrupt should use irq_set_vcpu_affinity */
> if (irqd_is_forwarded_to_vcpu(d))
> return -EINVAL;
>
> - /* lpi cannot be routed to a redistributor that is on a foreign node */
> - if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
> - if (its_dev->its->numa_node >= 0) {
> - cpu_mask = cpumask_of_node(its_dev->its->numa_node);
> - if (!cpumask_intersects(mask_val, cpu_mask))
> - return -EINVAL;
> - }
> - }
> -
> - cpu = cpumask_any_and(mask_val, cpu_mask);
> + if (!force)
> + cpu = its_select_cpu(d, mask_val);
> + else
> + cpu = cpumask_pick_least_loaded(d, mask_val);
>
> - if (cpu >= nr_cpu_ids)
> + if (cpu < 0 || cpu >= nr_cpu_ids)
> return -EINVAL;
Annotate missing code:
if (cpu < 0 || cpu >= nr_cpu_ids)
return -EINVAL;
if (cpu != its_dev->event_map.col_map[id]) {
its_inc_lpi_count(d, cpu);
its_dec_lpi_count(d, its_dev->event_map.col_map[id]);
target_col = &its_dev->its->collections[cpu];
its_send_movi(its_dev, target_col, id);
its_dev->event_map.col_map[id] = cpu;
irq_data_update_effective_affinity(d, cpumask_of(cpu));
}
So cpu may not be a member of mask_val. Hence the inconsistency of the
affinity list and effective affinity. We could just drop the AND of the
ITS node mask in its_select_cpu().
Anyway, I don't think that this should stop us testing.
Cheers,
John
next prev parent reply other threads:[~2020-03-18 12:22 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-16 11:54 [PATCH v3 0/2] irqchip/gic-v3-its: Balance LPI affinity across CPUs Marc Zyngier
2020-03-16 11:54 ` [PATCH v3 1/2] irqchip/gic-v3-its: Track LPI distribution on a per CPU basis Marc Zyngier
2020-03-16 11:54 ` [PATCH v3 2/2] irqchip/gic-v3-its: Balance initial LPI affinity across CPUs Marc Zyngier
2020-03-16 13:02 ` John Garry
2020-03-16 13:14 ` Marc Zyngier
2020-03-17 18:43 ` John Garry
2020-03-18 14:16 ` Marc Zyngier
2020-03-18 14:25 ` John Garry
2020-03-18 12:22 ` John Garry [this message]
2020-03-18 14:04 ` Marc Zyngier
2020-03-18 15:34 ` John Garry
2020-03-18 17:30 ` Marc Zyngier
2020-03-18 19:00 ` John Garry
2020-03-27 17:52 ` John Garry
2020-03-19 12:31 ` [PATCH v3 0/2] irqchip/gic-v3-its: Balance " John Garry
2020-03-27 17:47 ` John Garry
2020-04-01 11:33 ` John Garry
2020-05-14 12:05 ` John Garry
2020-05-15 10:14 ` Marc Zyngier
2020-05-15 11:50 ` John Garry
2020-05-15 15:37 ` Marc Zyngier
2020-05-15 16:15 ` John Garry
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