From: John Garry <john.garry@huawei.com>
To: Marc Zyngier <maz@kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: Jason Cooper <jason@lakedaemon.net>,
chenxiang <chenxiang66@hisilicon.com>,
Robin Murphy <robin.murphy@arm.com>,
"luojiaxing@huawei.com" <luojiaxing@huawei.com>,
Ming Lei <ming.lei@redhat.com>,
Zhou Wang <wangzhou1@hisilicon.com>,
Thomas Gleixner <tglx@linutronix.de>,
Will Deacon <will@kernel.org>
Subject: Re: [PATCH v3 0/2] irqchip/gic-v3-its: Balance LPI affinity across CPUs
Date: Wed, 1 Apr 2020 12:33:21 +0100 [thread overview]
Message-ID: <f2971d1c-50f8-bf5a-8b16-8d84a631b0ba@huawei.com> (raw)
In-Reply-To: <80b673a7-1097-c5fa-82c0-1056baa5309d@huawei.com>
Hi Marc,
> But I would also like to report some other unexpected behaviour for
> managed interrupts in this series - I'll reply directly to the specific
> patch for that.
>
So I made this change:
diff --git a/drivers/irqchip/irq-gic-v3-its.c
b/drivers/irqchip/irq-gic-v3-its.c
index 9199fb53c75c..ebbfc8d44d35 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1539,6 +1539,8 @@ static int its_set_affinity(struct irq_data *d,
const struct cpumask *mask_val,
if (irqd_is_forwarded_to_vcpu(d))
return -EINVAL;
+ its_dec_lpi_count(d, its_dev->event_map.col_map[id]);
+
if (!force)
cpu = its_select_cpu(d, mask_val);
else
@@ -1549,14 +1551,14 @@ static int its_set_affinity(struct irq_data *d,
const struct cpumask *mask_val,
/* don't set the affinity when the target cpu is same as
current one */
if (cpu != its_dev->event_map.col_map[id]) {
- its_inc_lpi_count(d, cpu);
- its_dec_lpi_count(d, its_dev->event_map.col_map[id]);
target_col = &its_dev->its->collections[cpu];
its_send_movi(its_dev, target_col, id);
its_dev->event_map.col_map[id] = cpu;
irq_data_update_effective_affinity(d, cpumask_of(cpu));
}
+ its_inc_lpi_count(d, cpu);
+
return IRQ_SET_MASK_OK_DONE;
}
Results look ok:
nvme.use_threaded_interrupts=1 =0*
Before 950K IOPs 1000K IOPs
After 1100K IOPs 1150K IOPs
* as mentioned before, this is quite unstable and causes lockups. JFYI,
there was an attempt to fix this:
https://lore.kernel.org/linux-nvme/20191209175622.1964-1-kbusch@kernel.org/
Thanks,
John
next prev parent reply other threads:[~2020-04-01 11:33 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-16 11:54 [PATCH v3 0/2] irqchip/gic-v3-its: Balance LPI affinity across CPUs Marc Zyngier
2020-03-16 11:54 ` [PATCH v3 1/2] irqchip/gic-v3-its: Track LPI distribution on a per CPU basis Marc Zyngier
2020-03-16 11:54 ` [PATCH v3 2/2] irqchip/gic-v3-its: Balance initial LPI affinity across CPUs Marc Zyngier
2020-03-16 13:02 ` John Garry
2020-03-16 13:14 ` Marc Zyngier
2020-03-17 18:43 ` John Garry
2020-03-18 14:16 ` Marc Zyngier
2020-03-18 14:25 ` John Garry
2020-03-18 12:22 ` John Garry
2020-03-18 14:04 ` Marc Zyngier
2020-03-18 15:34 ` John Garry
2020-03-18 17:30 ` Marc Zyngier
2020-03-18 19:00 ` John Garry
2020-03-27 17:52 ` John Garry
2020-03-19 12:31 ` [PATCH v3 0/2] irqchip/gic-v3-its: Balance " John Garry
2020-03-27 17:47 ` John Garry
2020-04-01 11:33 ` John Garry [this message]
2020-05-14 12:05 ` John Garry
2020-05-15 10:14 ` Marc Zyngier
2020-05-15 11:50 ` John Garry
2020-05-15 15:37 ` Marc Zyngier
2020-05-15 16:15 ` John Garry
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