Re: [RFC PATCH 0/3] Separate BE DAI HW constraints from FE ones

[Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>]

On 4/16/21 1:55 PM, Mark Brown wrote:
> On Fri, Apr 16, 2021 at 11:47:01AM -0500, Pierre-Louis Bossart wrote:
>> On 4/16/21 11:31 AM, Mark Brown wrote:
> 
>>> Not really written down that I can think of.  I think the next steps
>>> that I can think of right now are unfortunately bigger and harder ones,
>>> mainly working out a way to represent digital configuration as a graph
>>> that can be attached to/run in parallel with DAPM other people might
>>> have some better ideas though.  Sorry, I appreciate that this isn't
>>> super helpful :/
> 
>> I see a need for this in our future SoundWire/SDCA work. So far I was
>> planning to model the entities as 'widgets' and lets DAPM propagate
>> activation information for power management, however there are also bits of
>> information in 'Clusters' (number of channels and spatial relationships)
>> that could change dynamically and would be interesting to propagate across
>> entities, so that when we get a stream of data on the bus we know what it
>> is.
> 
> Yes, I was thinking along similar lines last time I looked at it - I was
> using the term digital domains.  You'd need some impedence matching
> objects for things like SRCs, and the ability to flag which
> configuration matters within a domain (eg, a lot of things will covert
> to the maximum supported bit width for internal operation so bit width
> only matters on external interfaces) but I think for a first pass we can
> get away with forcing everything other than what DPCM has as front ends
> into static configurations.

You lost me on the last sentence. did you mean "forcing everything into 
static configurations except for what DPCM has as front-ends"?

It may already be too late for static configurations, Intel, NXP and 
others have started to enable cases where the dailink configuration varies.

FWIW both the USB and SDCA class document are very careful with the 
notion of constraints and whether an entity is implemented in the analog 
or digital domains. There are 'clock sources' that may be used in 
specific terminals but no notion of explicit SRC in the graph to leave 
implementers a lot of freedom. There is a notion of 'Usage' that 
describes e.g. FullBand or WideBand without defining what the 
representation is. The bit width is also not described except where 
necessary (history buffers and external bus-facing interfaces). Like you 
said it's mostly the boundaries of the domains that matter.