Re: [patch V2 27/28] x86/speculation: Add seccomp Spectre v2 user space protection mode

From: Jiri Kosina <jikos@kernel.org>
To: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Linux List Kernel Mailing <linux-kernel@vger.kernel.org>,
	the arch/x86 maintainers <x86@kernel.org>,
	Peter Zijlstra <peterz@infradead.org>,
	Andrew Lutomirski <luto@kernel.org>,
	thomas.lendacky@amd.com, Josh Poimboeuf <jpoimboe@redhat.com>,
	Andrea Arcangeli <aarcange@redhat.com>,
	David Woodhouse <dwmw@amazon.co.uk>,
	Tim Chen <tim.c.chen@linux.intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	dave.hansen@intel.com,
	Casey Schaufler <casey.schaufler@intel.com>,
	"Mallick, Asit K" <asit.k.mallick@intel.com>,
	"Van De Ven, Arjan" <arjan@linux.intel.com>,
	jcm@redhat.com, longman9394@gmail.com,
	Greg KH <gregkh@linuxfoundation.org>,
	david.c.stewart@intel.com, Kees Cook <keescook@chromium.org>
Subject: Re: [patch V2 27/28] x86/speculation: Add seccomp Spectre v2 user space protection mode
Date: Sun, 25 Nov 2018 21:52:36 +0100 (CET)	[thread overview]
Message-ID: <nycvar.YFH.7.76.1811252147450.21108@cbobk.fhfr.pm> (raw)
In-Reply-To: <CAHk-=whtiX45YPjFPMFuktZ3WB23zqBZR-rL6RewrTyvrFj2Fw@mail.gmail.com>

On Sun, 25 Nov 2018, Linus Torvalds wrote:

> > The mitigation guide documents how STIPB works:
> >
> >    Setting bit 1 (STIBP) of the IA32_SPEC_CTRL MSR on a logical processor
> >    prevents the predicted targets of indirect branches on any logical
> >    processor of that core from being controlled by software that executes
> >    (or executed previously) on another logical processor of the same core.
> 
> Can we please just fix this stupid lie?
> 
> Yes, Intel calls it "STIBP" and tries to make it out to be about the
> indirect branch predictor being per-SMT thread.
> 
> But the reason it is unacceptable is apparently because in reality it just
> disables indirect branch prediction entirely. So yes, *technically* it's
> true that that limits indirect branch prediction to just a single SMT
> core, but in reality it is just a "go really slow" mode.
> 
> If STIBP had actually just keyed off the logical SMT thread, we wouldn't
> need to have worried about it in the first place.
> 
> So let's document reality rather than Intel's Pollyanna world-view.
> 
> Reality matters. It's why we had to go all this. Lying about things
> and making it appear like it's not a big deal was why the original
> patch made it through without people noticing.

Yeah, exactly; the documentation doesn't discourage STIBP use (well, the 
AMD one now actually does).

I am all in favor of documenting the truth rather than the documented 
behavior, but I guess without having a word from CPU folks, explaining how 
exactly this is implemented in reality, we can just guess based on 
observed symptoms (which is what we'll do anyway I guess if we don't get 
any better / more accurate wording).

Arjan, Tim, would you have a wording handy that would be guaranteed to 
describe the reality for the sake of changelog?

Thanks,

-- 
Jiri Kosina
SUSE Labs