[tip:perf/core] perf vendor events intel: Add uncore events for Skylake client

[tip:perf/core] perf vendor events intel: Add uncore events for Skylake client

[tip-bot for Andi Kleen]

Commit-ID:  92c6de0f10a80e4936fac04148bd3783a7c2b9f8
Gitweb:     http://git.kernel.org/tip/92c6de0f10a80e4936fac04148bd3783a7c2b9f8
Author:     Andi Kleen <ak@linux.intel.com>
AuthorDate: Wed, 29 Mar 2017 17:18:15 -0700
Committer:  Andi Kleen <ak@linux.intel.com>
CommitDate: Thu, 30 Mar 2017 13:35:32 -0700

perf vendor events intel: Add uncore events for Skylake client

Add V25 of Skylake uncore events

Cc: jolsa@kernel.org
Link: http://lkml.kernel.org/n/tip-00qmcrmq183x2qrj59g92fma@git.kernel.org
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
 .../arch/x86/{broadwell => skylake}/uncore.json    | 32 +++-------------------
 1 file changed, 4 insertions(+), 28 deletions(-)

diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore.json b/tools/perf/pmu-events/arch/x86/skylake/uncore.json
similarity index 86%
copy from tools/perf/pmu-events/arch/x86/broadwell/uncore.json
copy to tools/perf/pmu-events/arch/x86/skylake/uncore.json
index 28e1e15..dbc1932 100644
--- a/tools/perf/pmu-events/arch/x86/broadwell/uncore.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/uncore.json
@@ -50,18 +50,6 @@
   {
     "Unit": "CBO",
     "EventCode": "0x34",
-    "UMask": "0x11",
-    "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M",
-    "BriefDescription": "L3 Lookup read request that access cache and found line in M-state",
-    "PublicDescription": "L3 Lookup read request that access cache and found line in M-state.",
-    "Counter": "0,1",
-    "CounterMask": "0",
-    "Invert": "0",
-    "EdgeDetect": "0"
-  },
-  {
-    "Unit": "CBO",
-    "EventCode": "0x34",
     "UMask": "0x21",
     "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M",
     "BriefDescription": "L3 Lookup write request that access cache and found line in M-state",
@@ -184,21 +172,9 @@
     "EventCode": "0x80",
     "UMask": "0x01",
     "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL",
-    "BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
-    "PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
-    "Counter": "0,",
-    "CounterMask": "0",
-    "Invert": "0",
-    "EdgeDetect": "0"
-  },
-  {
-    "Unit": "iMPH-U",
-    "EventCode": "0x80",
-    "UMask": "0x02",
-    "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT",
-    "BriefDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
-    "PublicDescription": "Each cycle count number of 'valid' coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case.",
-    "Counter": "0,",
+    "BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
+    "PublicDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.",
+    "Counter": "0",
     "CounterMask": "0",
     "Invert": "0",
     "EdgeDetect": "0"
@@ -258,7 +234,7 @@
     "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST",
     "BriefDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.;",
     "PublicDescription": "Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC.",
-    "Counter": "0,",
+    "Counter": "0",
     "CounterMask": "1",
     "Invert": "0",
     "EdgeDetect": "0"