From: David Miller <davem@davemloft.net>
To: yash.shah@sifive.com
Cc: devicetree@vger.kernel.org, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
robh+dt@kernel.org, mark.rutland@arm.com,
nicolas.ferre@microchip.com, palmer@sifive.com,
aou@eecs.berkeley.edu, paul.walmsley@sifive.com, ynezz@true.cz,
sachin.ghadi@sifive.com
Subject: Re: [PATCH v3 0/2] Add macb support for SiFive FU540-C000
Date: Tue, 18 Jun 2019 22:02:51 -0400 (EDT) [thread overview]
Message-ID: <20190618.220251.295948387700018458.davem@davemloft.net> (raw)
In-Reply-To: <1560844568-4746-1-git-send-email-yash.shah@sifive.com>
From: Yash Shah <yash.shah@sifive.com>
Date: Tue, 18 Jun 2019 13:26:06 +0530
> On FU540, the management IP block is tightly coupled with the Cadence
> MACB IP block. It manages many of the boundary signals from the MACB IP
> This patchset controls the tx_clk input signal to the MACB IP. It
> switches between the local TX clock (125MHz) and PHY TX clocks. This
> is necessary to toggle between 1Gb and 100/10Mb speeds.
>
> Future patches may add support for monitoring or controlling other IP
> boundary signals.
>
> This patchset is mostly based on work done by
> Wesley Terpstra <wesley@sifive.com>
>
> This patchset is based on Linux v5.2-rc1 and tested on HiFive Unleashed
> board with additional board related patches needed for testing can be
> found at dev/yashs/ethernet_v3 branch of:
> https://github.com/yashshah7/riscv-linux.git
>
> Change History:
...
Series applied, thank you.
prev parent reply other threads:[~2019-06-19 2:03 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-18 7:56 [PATCH v3 0/2] Add macb support for SiFive FU540-C000 Yash Shah
2019-06-18 7:56 ` [PATCH v3 1/2] macb: bindings doc: add sifive fu540-c000 binding Yash Shah
2019-06-18 7:56 ` [PATCH v3 2/2] macb: Add support for SiFive FU540-C000 Yash Shah
2019-06-18 23:27 ` [PATCH v3 0/2] Add macb " Atish Patra
2019-06-19 2:02 ` David Miller [this message]
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