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From: Weiwei Li <liweiwei@iscas.ac.cn>
To: Kaiwen Xue <kaiwenx@rivosinc.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: liweiwei@iscas.ac.cn, Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bin.meng@windriver.com>,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
	Atish Kumar Patra <atishp@atishpatra.org>,
	Kaiwen Xue <kaiwenx@andrew.cmu.edu>
Subject: Re: [PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties
Date: Wed, 19 Jul 2023 09:20:42 +0800	[thread overview]
Message-ID: <07409bc6-dc55-abd6-f527-2797aa251a88@iscas.ac.cn> (raw)
In-Reply-To: <d0e7d84180afec116b9fc54ef72fba1d7d8ff345.1689631639.git.kaiwenx@rivosinc.com>


On 2023/7/19 06:47, Kaiwen Xue wrote:
> This adds the properties for ISA extension smcntrpmf. Patches
> implementing it will follow.
>
> Signed-off-by: Kaiwen Xue <kaiwenx@andrew.cmu.edu>
> Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
> ---
>   target/riscv/cpu.c     | 2 ++
>   target/riscv/cpu_cfg.h | 1 +
>   2 files changed, 3 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9339c0241d..31a1862561 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -132,6 +132,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
>       ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
>       ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
>       ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
> +    ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
>       ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
>       ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
>       ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
> @@ -1753,6 +1754,7 @@ static Property riscv_cpu_extensions[] = {
>       /* Defaults for standard extensions */
>       DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
>       DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
> +    DEFINE_PROP_BOOL("smcntrpmf", RISCVCPU, cfg.ext_smcntrpmf, false),

Normally, property should be exposed to user at last after the function 
is implemented.

Regards,

Weiwei Li

>       DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
>       DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
>       DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
> diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> index 2bd9510ba3..424246cbec 100644
> --- a/target/riscv/cpu_cfg.h
> +++ b/target/riscv/cpu_cfg.h
> @@ -69,6 +69,7 @@ struct RISCVCPUConfig {
>       bool ext_zihintpause;
>       bool ext_smstateen;
>       bool ext_sstc;
> +    bool ext_smcntrpmf;
>       bool ext_svadu;
>       bool ext_svinval;
>       bool ext_svnapot;



  reply	other threads:[~2023-07-19  1:21 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-18 22:47 [PATCH 0/3] risc-v: Add ISA extension smcntrpmf support Kaiwen Xue
2023-07-18 22:47 ` [PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties Kaiwen Xue
2023-07-19  1:20   ` Weiwei Li [this message]
2023-07-22  0:13     ` Kevin Xue
2023-07-18 22:47 ` [PATCH 2/3] target/riscv: Add cycle & instret privilege mode filtering definitions Kaiwen Xue
2023-07-18 22:47 ` [PATCH 3/3] target/riscv: Add cycle & instret privilege mode filtering support Kaiwen Xue
2023-07-19  1:25   ` Weiwei Li
2023-07-22  0:25     ` Kevin Xue

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