From: Kaiwen Xue <kaiwenx@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: Kaiwen Xue <kaiwenx@rivosinc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Atish Kumar Patra <atishp@atishpatra.org>,
Kaiwen Xue <kaiwenx@andrew.cmu.edu>
Subject: [PATCH 0/3] risc-v: Add ISA extension smcntrpmf support
Date: Tue, 18 Jul 2023 15:47:42 -0700 [thread overview]
Message-ID: <cover.1689631639.git.kaiwenx@rivosinc.com> (raw)
This patch series adds the support for RISC-V ISA extension smcntrpmf (cycle and
privilege mode filtering) [1]. QEMU only calculates dummy cycles and
instructions, so there is no actual means to stop the icount in QEMU. Therefore,
this series only add the read/write behavior of the relevant CSRs such that the
implemented firmware support [2] can work without causing unnecessary illegal
instruction exceptions.
[1] https://github.com/riscv/riscv-smcntrpmf
[2] https://github.com/rivosinc/opensbi/tree/dev/kaiwenx/smcntrpmf_upstream
Kaiwen Xue (3):
target/riscv: Add cycle & instret privilege mode filtering properties
target/riscv: Add cycle & instret privilege mode filtering definitions
target/riscv: Add cycle & instret privilege mode filtering support
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 6 ++++
target/riscv/cpu_bits.h | 29 ++++++++++++++++
target/riscv/cpu_cfg.h | 1 +
target/riscv/csr.c | 73 +++++++++++++++++++++++++++++++++++++++++
5 files changed, 111 insertions(+)
--
2.34.1
next reply other threads:[~2023-07-19 1:23 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-18 22:47 Kaiwen Xue [this message]
2023-07-18 22:47 ` [PATCH 1/3] target/riscv: Add cycle & instret privilege mode filtering properties Kaiwen Xue
2023-07-19 1:20 ` Weiwei Li
2023-07-22 0:13 ` Kevin Xue
2023-07-18 22:47 ` [PATCH 2/3] target/riscv: Add cycle & instret privilege mode filtering definitions Kaiwen Xue
2023-07-18 22:47 ` [PATCH 3/3] target/riscv: Add cycle & instret privilege mode filtering support Kaiwen Xue
2023-07-19 1:25 ` Weiwei Li
2023-07-22 0:25 ` Kevin Xue
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