From: David Hildenbrand <david@redhat.com>
To: qemu-devel@nongnu.org
Cc: Thomas Huth <thuth@redhat.com>,
Janosch Frank <frankja@linux.ibm.com>,
David Hildenbrand <david@redhat.com>,
Cornelia Huck <cohuck@redhat.com>,
Halil Pasic <pasic@linux.ibm.com>,
Christian Borntraeger <borntraeger@de.ibm.com>,
qemu-s390x@nongnu.org, Richard Henderson <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH-for-4.2 v2 6/6] s390x/mmu: Factor out storage key handling
Date: Wed, 14 Aug 2019 09:23:55 +0200 [thread overview]
Message-ID: <20190814072355.15333-7-david@redhat.com> (raw)
In-Reply-To: <20190814072355.15333-1-david@redhat.com>
Factor it out, add a comment how it all works, and also use it in the
REAL MMU.
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
---
target/s390x/mmu_helper.c | 113 +++++++++++++++++++++++---------------
1 file changed, 69 insertions(+), 44 deletions(-)
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
index 6cc81a29b6..e125837d68 100644
--- a/target/s390x/mmu_helper.c
+++ b/target/s390x/mmu_helper.c
@@ -334,6 +334,73 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
return r;
}
+static void mmu_handle_skey(target_ulong addr, int rw, int *flags)
+{
+ static S390SKeysClass *skeyclass;
+ static S390SKeysState *ss;
+ uint8_t key;
+ int rc;
+
+ if (unlikely(!ss)) {
+ ss = s390_get_skeys_device();
+ skeyclass = S390_SKEYS_GET_CLASS(ss);
+ }
+
+ /*
+ * Whenever we create a new TLB entry, we set the storage key reference
+ * bit. In case we allow write accesses, we set the storage key change
+ * bit. Whenever the guest changes the storage key, we have to flush the
+ * TLBs of all CPUs (the whole TLB or all affected entries), so that the
+ * next reference/change will result in an MMU fault and make us properly
+ * update the storage key here.
+ *
+ * Note 1: "record of references ... is not necessarily accurate",
+ * "change bit may be set in case no storing has occurred".
+ * -> We can set reference/change bits even on exceptions.
+ * Note 2: certain accesses seem to ignore storage keys. For example,
+ * DAT translation does not set reference bits for table accesses.
+ *
+ * TODO: key-controlled protection. Only CPU accesses make use of the
+ * PSW key. CSS accesses are different - we have to pass in the key.
+ *
+ * TODO: we have races between getting and setting the key.
+ */
+ if (addr < ram_size) {
+ rc = skeyclass->get_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
+ if (rc) {
+ trace_get_skeys_nonzero(rc);
+ return;
+ }
+
+ switch (rw) {
+ case MMU_DATA_LOAD:
+ case MMU_INST_FETCH:
+ /*
+ * The TLB entry has to remain write-protected on read-faults if
+ * the storage key does not indicate a change already. Otherwise
+ * we might miss setting the change bit on write accesses.
+ */
+ if (!(key & SK_C)) {
+ *flags &= ~PAGE_WRITE;
+ }
+ break;
+ case MMU_DATA_STORE:
+ key |= SK_C;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ /* Any store/fetch sets the reference bit */
+ key |= SK_R;
+
+ rc = skeyclass->set_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
+ if (rc) {
+ trace_set_skeys_nonzero(rc);
+ }
+ }
+}
+
/**
* Translate a virtual (logical) address into a physical (absolute) address.
* @param vaddr the virtual address
@@ -347,16 +414,9 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
target_ulong *raddr, int *flags, bool exc)
{
- static S390SKeysState *ss;
- static S390SKeysClass *skeyclass;
uint64_t asce;
- uint8_t key;
int r;
- if (unlikely(!ss)) {
- ss = s390_get_skeys_device();
- skeyclass = S390_SKEYS_GET_CLASS(ss);
- }
*flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
if (is_low_address(vaddr & TARGET_PAGE_MASK) && lowprot_enabled(env, asc)) {
@@ -413,42 +473,7 @@ nodat:
/* Convert real address -> absolute address */
*raddr = mmu_real2abs(env, *raddr);
- if (*raddr < ram_size) {
- r = skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key);
- if (r) {
- trace_get_skeys_nonzero(r);
- return 0;
- }
-
- switch (rw) {
- case MMU_DATA_LOAD:
- case MMU_INST_FETCH:
- /*
- * The TLB entry has to remain write-protected on read-faults if
- * the storage key does not indicate a change already. Otherwise
- * we might miss setting the change bit on write accesses.
- */
- if (!(key & SK_C)) {
- *flags &= ~PAGE_WRITE;
- }
- break;
- case MMU_DATA_STORE:
- key |= SK_C;
- break;
- default:
- g_assert_not_reached();
- }
-
- /* Any store/fetch sets the reference bit */
- key |= SK_R;
-
- r = skeyclass->set_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key);
- if (r) {
- trace_set_skeys_nonzero(r);
- return 0;
- }
- }
-
+ mmu_handle_skey(*raddr, rw, flags);
return 0;
}
@@ -566,6 +591,6 @@ int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw,
*addr = mmu_real2abs(env, raddr & TARGET_PAGE_MASK);
- /* TODO: storage key handling */
+ mmu_handle_skey(*addr, rw, flags);
return 0;
}
--
2.21.0
next prev parent reply other threads:[~2019-08-14 7:29 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-14 7:23 [Qemu-devel] [PATCH-for-4.2 v2 0/6] s390x/mmu: Storage key reference and change bit handling David Hildenbrand
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 1/6] s390x/mmu: ASC selection in s390_cpu_get_phys_page_debug() David Hildenbrand
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 2/6] s390x/tcg: Rework MMU selection for instruction fetches David Hildenbrand
2019-08-14 17:44 ` [Qemu-devel] [qemu-s390x] " Thomas Huth
2019-08-15 15:43 ` [Qemu-devel] " Cornelia Huck
2019-08-15 16:52 ` David Hildenbrand
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 3/6] s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE David Hildenbrand
2019-08-14 10:06 ` Alex Bennée
2019-08-14 10:21 ` David Hildenbrand
2019-08-14 10:44 ` Alex Bennée
2019-08-14 10:51 ` David Hildenbrand
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 4/6] s390x/mmu: Trace the right value if setting/getting the storage key fails David Hildenbrand
2019-08-14 17:50 ` [Qemu-devel] [qemu-s390x] " Thomas Huth
2019-08-15 15:39 ` Cornelia Huck
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 5/6] s390x/mmu: Better storage key reference and change bit handling David Hildenbrand
2019-08-14 7:23 ` David Hildenbrand [this message]
2019-08-14 18:01 ` [Qemu-devel] [qemu-s390x] [PATCH-for-4.2 v2 6/6] s390x/mmu: Factor out storage key handling Thomas Huth
2019-08-14 18:18 ` David Hildenbrand
2019-08-19 16:36 ` [Qemu-devel] [PATCH-for-4.2 v2 0/6] s390x/mmu: Storage key reference and change bit handling Cornelia Huck
2019-08-19 16:37 ` Cornelia Huck
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