From: David Hildenbrand <david@redhat.com>
To: Thomas Huth <thuth@redhat.com>, qemu-devel@nongnu.org
Cc: Janosch Frank <frankja@linux.ibm.com>,
Cornelia Huck <cohuck@redhat.com>,
Halil Pasic <pasic@linux.ibm.com>,
Christian Borntraeger <borntraeger@de.ibm.com>,
qemu-s390x@nongnu.org, Richard Henderson <rth@twiddle.net>
Subject: Re: [Qemu-devel] [qemu-s390x] [PATCH-for-4.2 v2 6/6] s390x/mmu: Factor out storage key handling
Date: Wed, 14 Aug 2019 20:18:58 +0200 [thread overview]
Message-ID: <34726977-5ef4-7747-61de-c77313ad0f62@redhat.com> (raw)
In-Reply-To: <421d4297-326a-505d-a204-57f7a7211a33@redhat.com>
On 14.08.19 20:01, Thomas Huth wrote:
> On 8/14/19 9:23 AM, David Hildenbrand wrote:
>> Factor it out, add a comment how it all works, and also use it in the
>> REAL MMU.
>>
>> Reviewed-by: Cornelia Huck <cohuck@redhat.com>
>> Signed-off-by: David Hildenbrand <david@redhat.com>
>> ---
>> target/s390x/mmu_helper.c | 113 +++++++++++++++++++++++---------------
>> 1 file changed, 69 insertions(+), 44 deletions(-)
>>
>> diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
>> index 6cc81a29b6..e125837d68 100644
>> --- a/target/s390x/mmu_helper.c
>> +++ b/target/s390x/mmu_helper.c
>> @@ -334,6 +334,73 @@ static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
>> return r;
>> }
>>
>> +static void mmu_handle_skey(target_ulong addr, int rw, int *flags)
>> +{
>> + static S390SKeysClass *skeyclass;
>> + static S390SKeysState *ss;
>> + uint8_t key;
>> + int rc;
>> +
>> + if (unlikely(!ss)) {
>> + ss = s390_get_skeys_device();
>> + skeyclass = S390_SKEYS_GET_CLASS(ss);
>> + }
>> +
>> + /*
>> + * Whenever we create a new TLB entry, we set the storage key reference
>> + * bit. In case we allow write accesses, we set the storage key change
>> + * bit. Whenever the guest changes the storage key, we have to flush the
>> + * TLBs of all CPUs (the whole TLB or all affected entries), so that the
>> + * next reference/change will result in an MMU fault and make us properly
>> + * update the storage key here.
>> + *
>> + * Note 1: "record of references ... is not necessarily accurate",
>> + * "change bit may be set in case no storing has occurred".
>> + * -> We can set reference/change bits even on exceptions.
>> + * Note 2: certain accesses seem to ignore storage keys. For example,
>> + * DAT translation does not set reference bits for table accesses.
>> + *
>> + * TODO: key-controlled protection. Only CPU accesses make use of the
>> + * PSW key. CSS accesses are different - we have to pass in the key.
>> + *
>> + * TODO: we have races between getting and setting the key.
>> + */
>> + if (addr < ram_size) {
>
> If you want to get rid of some indentation, you could do an early return
> if (addr >= ram_size) here instead.
Right, that makes a lot of sense, will do this. Thanks!
>
> Anyway, good idea to refactor this code, so also in its current shape:
>
> Reviewed-by: Thomas Huth <thuth@redhat.com>
>
--
Thanks,
David / dhildenb
next prev parent reply other threads:[~2019-08-14 18:20 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-14 7:23 [Qemu-devel] [PATCH-for-4.2 v2 0/6] s390x/mmu: Storage key reference and change bit handling David Hildenbrand
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 1/6] s390x/mmu: ASC selection in s390_cpu_get_phys_page_debug() David Hildenbrand
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 2/6] s390x/tcg: Rework MMU selection for instruction fetches David Hildenbrand
2019-08-14 17:44 ` [Qemu-devel] [qemu-s390x] " Thomas Huth
2019-08-15 15:43 ` [Qemu-devel] " Cornelia Huck
2019-08-15 16:52 ` David Hildenbrand
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 3/6] s390x/tcg: Flush the TLB of all CPUs on SSKE and RRBE David Hildenbrand
2019-08-14 10:06 ` Alex Bennée
2019-08-14 10:21 ` David Hildenbrand
2019-08-14 10:44 ` Alex Bennée
2019-08-14 10:51 ` David Hildenbrand
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 4/6] s390x/mmu: Trace the right value if setting/getting the storage key fails David Hildenbrand
2019-08-14 17:50 ` [Qemu-devel] [qemu-s390x] " Thomas Huth
2019-08-15 15:39 ` Cornelia Huck
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 5/6] s390x/mmu: Better storage key reference and change bit handling David Hildenbrand
2019-08-14 7:23 ` [Qemu-devel] [PATCH-for-4.2 v2 6/6] s390x/mmu: Factor out storage key handling David Hildenbrand
2019-08-14 18:01 ` [Qemu-devel] [qemu-s390x] " Thomas Huth
2019-08-14 18:18 ` David Hildenbrand [this message]
2019-08-19 16:36 ` [Qemu-devel] [PATCH-for-4.2 v2 0/6] s390x/mmu: Storage key reference and change bit handling Cornelia Huck
2019-08-19 16:37 ` Cornelia Huck
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=34726977-5ef4-7747-61de-c77313ad0f62@redhat.com \
--to=david@redhat.com \
--cc=borntraeger@de.ibm.com \
--cc=cohuck@redhat.com \
--cc=frankja@linux.ibm.com \
--cc=pasic@linux.ibm.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-s390x@nongnu.org \
--cc=rth@twiddle.net \
--cc=thuth@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).