From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PATCH 06/19] target/arm: Rename isar_feature_aa32_fpdp_v2
Date: Fri, 14 Feb 2020 10:15:34 -0800 [thread overview]
Message-ID: <20200214181547.21408-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200214181547.21408-1-richard.henderson@linaro.org>
The old name, isar_feature_aa32_fpdp, does not reflect
that the test includes VFPv2. We will introduce another
feature tests for VFPv3.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 4 ++--
target/arm/translate-vfp.inc.c | 40 +++++++++++++++++-----------------
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 85b90eaed2..5f08cbd2d8 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3429,9 +3429,9 @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
-static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
+static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id)
{
- /* Return true if CPU supports double precision floating point */
+ /* Return true if CPU supports double precision floating point, VFPv2 */
return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
}
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 96a1d727c6..5290828d0d 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -206,7 +206,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -339,7 +339,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -425,7 +425,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -488,7 +488,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
return false;
}
- if (dp && !dc_isar_feature(aa32_fpdp, s)) {
+ if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1313,7 +1313,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1462,7 +1462,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1826,7 +1826,7 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -1925,7 +1925,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2069,7 +2069,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2142,7 +2142,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2208,7 +2208,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2268,7 +2268,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2329,7 +2329,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2388,7 +2388,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2416,7 +2416,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2444,7 +2444,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2498,7 +2498,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2538,7 +2538,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2631,7 +2631,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
@@ -2727,7 +2727,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
return false;
}
- if (!dc_isar_feature(aa32_fpdp, s)) {
+ if (!dc_isar_feature(aa32_fpdp_v2, s)) {
return false;
}
--
2.20.1
next prev parent reply other threads:[~2020-02-14 18:22 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-14 18:15 [PATCH 00/19] target/arm: vfp feature and decodetree cleanup Richard Henderson
2020-02-14 18:15 ` [PATCH 01/19] target/arm: Fix field extract from MVFR[0-2] Richard Henderson
2020-02-14 18:29 ` Philippe Mathieu-Daudé
2020-02-14 18:35 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 02/19] target/arm: Rename isar_feature_aa32_simd_r32 Richard Henderson
2020-02-14 18:50 ` Philippe Mathieu-Daudé
2020-02-21 15:58 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 03/19] target/arm: Use isar_feature_aa32_simd_r32 more places Richard Henderson
2020-02-21 16:02 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 04/19] target/arm: Set MVFR0.FPSP for ARMv5 cpus Richard Henderson
2020-02-21 16:02 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 05/19] target/arm: Add isar_feature_aa32_simd_r16 Richard Henderson
2020-02-21 16:01 ` Peter Maydell
2020-02-14 18:15 ` Richard Henderson [this message]
2020-02-14 18:51 ` [PATCH 06/19] target/arm: Rename isar_feature_aa32_fpdp_v2 Philippe Mathieu-Daudé
2020-02-14 18:15 ` [PATCH 07/19] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Richard Henderson
2020-02-21 16:03 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 08/19] target/arm: Perform fpdp_v2 check first Richard Henderson
2020-02-21 16:04 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 09/19] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Richard Henderson
2020-02-21 16:05 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 10/19] target/arm: Add missing checks for fpsp_v2 Richard Henderson
2020-02-21 16:05 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 11/19] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Richard Henderson
2020-02-20 16:37 ` Peter Maydell
2020-02-20 16:41 ` Peter Maydell
2020-02-20 17:55 ` Richard Henderson
2020-02-14 18:15 ` [PATCH 12/19] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn Richard Henderson
2020-02-20 17:19 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 13/19] target/arm: Move VLLDM and VLSTM to vfp.decode Richard Henderson
2020-02-20 17:02 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 14/19] target/arm: Move the vfp decodetree calls next to the base isa Richard Henderson
2020-02-20 17:16 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 15/19] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP Richard Henderson
2020-02-20 17:32 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 16/19] target/arm: Remove ARM_FEATURE_VFP* Richard Henderson
2020-02-20 17:33 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 17/19] target/arm: Add formats for some vfp 2 and 3-register insns Richard Henderson
2020-02-20 17:40 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 18/19] target/arm: Split VFM decode Richard Henderson
2020-02-20 17:45 ` Peter Maydell
2020-02-14 18:15 ` [PATCH 19/19] target/arm: Split VMINMAXNM decode Richard Henderson
2020-02-20 17:49 ` Peter Maydell
2020-02-14 20:11 ` [PATCH 00/19] target/arm: vfp feature and decodetree cleanup no-reply
2020-02-20 17:52 ` Peter Maydell
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