From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>,
Frank Chang <frank.chang@sifive.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL
Date: Wed, 22 Jul 2020 17:15:38 +0800 [thread overview]
Message-ID: <20200722091641.8834-16-frank.chang@sifive.com> (raw)
In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Introduce the concepts of fractional LMUL, EEW and EMUL for RVV 0.9.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu.h | 16 ++++++++++------
target/riscv/insn_trans/trans_rvv.inc.c | 17 ++++++++++++++---
target/riscv/internals.h | 11 +++++++++--
target/riscv/translate.c | 4 ++++
target/riscv/vector_helper.c | 10 ++++++++--
5 files changed, 45 insertions(+), 13 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0a175151da..a16c6ed8e6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -96,8 +96,9 @@ typedef struct CPURISCVState CPURISCVState;
FIELD(VTYPE, VLMUL, 0, 2)
FIELD(VTYPE, VSEW, 2, 3)
-FIELD(VTYPE, VEDIV, 5, 2)
-FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
+FIELD(VTYPE, VFLMUL, 5, 1)
+FIELD(VTYPE, VEDIV, 8, 9)
+FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
@@ -368,9 +369,10 @@ typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
-FIELD(TB_FLAGS, LMUL, 3, 2)
-FIELD(TB_FLAGS, SEW, 5, 3)
-FIELD(TB_FLAGS, VILL, 8, 1)
+FIELD(TB_FLAGS, LMUL, 3, 3)
+FIELD(TB_FLAGS, SEW, 6, 3)
+/* Skip MSTATUS_VS (0x600) fields */
+FIELD(TB_FLAGS, VILL, 11, 1)
/*
* A simplification for VLMAX
@@ -399,12 +401,14 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
if (riscv_has_ext(env, RVV)) {
uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
+
flags = FIELD_DP32(flags, TB_FLAGS, VILL,
FIELD_EX64(env->vtype, VTYPE, VILL));
flags = FIELD_DP32(flags, TB_FLAGS, SEW,
FIELD_EX64(env->vtype, VTYPE, VSEW));
flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
- FIELD_EX64(env->vtype, VTYPE, VLMUL));
+ (FIELD_EX64(env->vtype, VTYPE, VFLMUL) << 2)
+ | FIELD_EX64(env->vtype, VTYPE, VLMUL));
flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
} else {
flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 018a134599..f6f0954c60 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -249,6 +249,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
}
@@ -301,6 +302,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
}
@@ -387,6 +389,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
}
@@ -425,6 +428,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
data = FIELD_DP32(data, VDATA, NF, a->nf);
fn = fns[seq][s->sew];
if (fn == NULL) {
@@ -516,6 +520,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
}
@@ -559,6 +564,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
}
@@ -637,6 +643,7 @@ static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
data = FIELD_DP32(data, VDATA, NF, a->nf);
return ldff_trans(a->rd, a->rs1, data, fn, s);
}
@@ -746,6 +753,7 @@ static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA, SEW, s->sew);
data = FIELD_DP32(data, VDATA, WD, a->wd);
return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
@@ -1644,7 +1652,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
vreg_ofs(s, a->rs1),
MAXSZ(s), MAXSZ(s));
} else {
- uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
static gen_helper_gvec_2_ptr * const fns[4] = {
gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
@@ -1682,7 +1691,8 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
TCGv_i32 desc ;
TCGv_i64 s1_i64 = tcg_temp_new_i64();
TCGv_ptr dest = tcg_temp_new_ptr();
- uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
static gen_helper_vmv_vx * const fns[4] = {
gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
@@ -1720,7 +1730,8 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
TCGv_i32 desc;
TCGv_i64 s1;
TCGv_ptr dest;
- uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+ uint32_t data = 0;
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
static gen_helper_vmv_vx * const fns[4] = {
gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 89fc0753bc..eaf792db5b 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -24,8 +24,9 @@
/* share data between vector helpers and decode code */
FIELD(VDATA, VM, 0, 1)
FIELD(VDATA, LMUL, 1, 3)
-FIELD(VDATA, NF, 4, 4)
-FIELD(VDATA, WD, 4, 1)
+FIELD(VDATA, SEW, 4, 3)
+FIELD(VDATA, NF, 7, 4)
+FIELD(VDATA, WD, 7, 1)
/* float point classify helpers */
target_ulong fclass_h(uint64_t frs1);
@@ -37,4 +38,10 @@ target_ulong fclass_d(uint64_t frs1);
#define SEW32 2
#define SEW64 3
+/* table to convert fractional LMUL value */
+static const float flmul_table[8] = {
+ 1, 2, 4, 8, /* LMUL */
+ -1, /* reserved */
+ 0.125, 0.25, 0.5 /* fractional LMUL */
+};
#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 7593b41a1f..72eb7c2e74 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -60,6 +60,9 @@ typedef struct DisasContext {
/* vector extension */
bool vill;
uint8_t lmul;
+ float flmul;
+ uint8_t eew;
+ float emul;
uint8_t sew;
uint16_t vlen;
bool vl_eq_vlmax;
@@ -823,6 +826,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
+ ctx->flmul = flmul_table[ctx->lmul];
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 6545f91732..a7963c3a2b 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -86,9 +86,15 @@ static inline uint32_t vext_vm(uint32_t desc)
return FIELD_EX32(simd_data(desc), VDATA, VM);
}
-static inline uint32_t vext_lmul(uint32_t desc)
+static inline uint32_t vext_sew(uint32_t desc)
{
- return FIELD_EX32(simd_data(desc), VDATA, LMUL);
+ return 1 << (FIELD_EX32(simd_data(desc), VDATA, SEW) + 3);
+}
+
+static inline float vext_vflmul(uint32_t desc)
+{
+ uint32_t lmul = FIELD_EX32(simd_data(desc), VDATA, LMUL);
+ return flmul_table[lmul];
}
static uint32_t vext_wd(uint32_t desc)
--
2.17.1
next prev parent reply other threads:[~2020-07-22 9:23 UTC|newest]
Thread overview: 147+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-22 9:15 [RFC v2 00/76] target/riscv: support vector extension v0.9 frank.chang
2020-07-22 9:15 ` [RFC v2 01/76] target/riscv: drop vector 0.7.1 support frank.chang
2020-07-22 16:37 ` Alistair Francis
2020-07-27 19:54 ` Palmer Dabbelt
2020-07-27 19:55 ` Alistair Francis
2020-07-30 8:07 ` Frank Chang
2020-07-30 12:27 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 02/76] target/riscv: rvv-0.9: support vector 0.9 frank.chang
2020-07-22 16:13 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion frank.chang
2020-07-22 16:18 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() frank.chang
2020-07-22 9:15 ` [RFC v2 05/76] target/riscv: fix return value of do_opivx_widen() frank.chang
2020-07-22 9:15 ` [RFC v2 06/76] target/riscv: fix vill bit index in vtype register frank.chang
2020-07-22 9:15 ` [RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2020-07-22 16:19 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field frank.chang
2020-07-22 16:33 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus " frank.chang
2020-07-22 16:34 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status frank.chang
2020-07-22 16:53 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register frank.chang
2020-07-22 16:54 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register frank.chang
2020-07-22 16:57 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register frank.chang
2020-07-22 16:58 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 14/76] target/riscv: rvv-0.9: remove MLEN calculations frank.chang
2020-07-22 17:04 ` Richard Henderson
2020-07-22 9:15 ` frank.chang [this message]
2020-07-22 17:30 ` [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL Richard Henderson
2020-07-23 2:11 ` Frank Chang
2020-07-22 9:15 ` [RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA frank.chang
2020-07-22 18:00 ` Richard Henderson
2020-07-23 2:18 ` Frank Chang
2020-07-22 9:15 ` [RFC v2 17/76] target/riscv: rvv-0.9: update check functions frank.chang
2020-07-22 9:15 ` [RFC v2 18/76] target/riscv: introduce more imm value modes in translator functions frank.chang
2020-07-22 18:08 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper frank.chang
2020-07-22 19:15 ` Richard Henderson
2020-07-23 7:13 ` Frank Chang
2020-07-23 16:14 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans frank.chang
2020-07-22 9:15 ` [RFC v2 21/76] target/riscv: rvv-0.9: configure instructions frank.chang
2020-07-22 20:00 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 22/76] target/riscv: rvv-0.9: stride load and store instructions frank.chang
2020-07-22 9:15 ` [RFC v2 23/76] target/riscv: rvv-0.9: index " frank.chang
2020-07-22 9:15 ` [RFC v2 24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns frank.chang
2020-07-22 9:15 ` [RFC v2 25/76] target/riscv: rvv-0.9: fault-only-first unit stride load frank.chang
2020-07-22 9:15 ` [RFC v2 26/76] target/riscv: rvv-0.9: amo operations frank.chang
2020-07-22 9:15 ` [RFC v2 27/76] target/riscv: rvv-0.9: load/store whole register instructions frank.chang
2020-07-29 20:30 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns frank.chang
2020-07-30 12:44 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation frank.chang
2020-07-30 12:52 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 30/76] target/riscv: rvv-0.9: floating-point square-root instruction frank.chang
2020-07-30 13:02 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 31/76] target/riscv: rvv-0.9: floating-point classify instructions frank.chang
2020-07-30 13:02 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 32/76] target/riscv: rvv-0.9: mask population count instruction frank.chang
2020-07-30 13:05 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction frank.chang
2020-07-30 13:13 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions frank.chang
2020-07-30 13:26 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 35/76] target/riscv: rvv-0.9: iota instruction frank.chang
2020-07-30 13:29 ` Richard Henderson
2020-07-22 9:15 ` [RFC v2 36/76] target/riscv: rvv-0.9: element index instruction frank.chang
2020-07-30 13:30 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended frank.chang
2020-07-30 13:43 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions frank.chang
2020-07-22 9:16 ` [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions frank.chang
2020-07-30 14:50 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction frank.chang
2020-07-30 19:57 ` Richard Henderson
2020-07-30 20:05 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions frank.chang
2020-07-30 20:03 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 42/76] target/riscv: rvv-0.9: whole register " frank.chang
2020-07-30 20:14 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions frank.chang
2020-07-30 20:35 ` Richard Henderson
2020-07-31 10:17 ` Frank Chang
2020-07-31 17:30 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions frank.chang
2020-07-30 20:45 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 45/76] target/riscv: rvv-0.9: single-width bit shift instructions frank.chang
2020-07-30 20:47 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 46/76] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow frank.chang
2020-07-22 9:16 ` [RFC v2 47/76] target/riscv: rvv-0.9: narrowing integer right shift instructions frank.chang
2020-07-30 21:02 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 48/76] target/riscv: rvv-0.9: widening integer multiply-add instructions frank.chang
2020-07-30 21:04 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 49/76] target/riscv: rvv-0.9: quad-widening " frank.chang
2020-07-30 21:19 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions frank.chang
2020-07-30 21:24 ` Richard Henderson
2020-08-04 2:40 ` Frank Chang
2020-08-05 16:48 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 51/76] target/riscv: rvv-0.9: integer comparison instructions frank.chang
2020-07-30 21:30 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 52/76] fpu: implement full set compare for fp16 frank.chang
2020-07-22 11:35 ` Alex Bennée
2020-07-22 9:16 ` [RFC v2 53/76] target/riscv: use softfloat lib float16 comparison functions frank.chang
2020-07-30 21:32 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 54/76] target/riscv: rvv-0.9: floating-point compare instructions frank.chang
2020-07-22 9:16 ` [RFC v2 55/76] target/riscv: rvv-0.9: single-width integer reduction instructions frank.chang
2020-07-22 9:16 ` [RFC v2 56/76] target/riscv: rvv-0.9: widening " frank.chang
2020-07-31 15:13 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 57/76] target/riscv: rvv-0.9: mask-register logical instructions frank.chang
2020-07-22 9:16 ` [RFC v2 58/76] target/riscv: rvv-0.9: slide instructions frank.chang
2020-07-31 15:57 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 59/76] target/riscv: rvv-0.9: floating-point " frank.chang
2020-07-31 16:05 ` Richard Henderson
2020-08-03 10:35 ` Frank Chang
2020-08-03 18:57 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 60/76] target/riscv: rvv-0.9: narrowing fixed-point clip instructions frank.chang
2020-07-31 16:07 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 61/76] target/riscv: rvv-0.9: floating-point/integer type-convert instructions frank.chang
2020-07-31 16:32 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 62/76] target/riscv: rvv-0.9: single-width floating-point reduction frank.chang
2020-07-31 16:45 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 63/76] target/riscv: rvv-0.9: widening floating-point reduction instructions frank.chang
2020-07-22 9:16 ` [RFC v2 64/76] target/riscv: rvv-0.9: single-width scaling shift instructions frank.chang
2020-07-31 16:59 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 65/76] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add frank.chang
2020-07-31 17:02 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 66/76] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf frank.chang
2020-07-31 17:03 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 67/76] target/riscv: rvv-0.9: remove integer extract instruction frank.chang
2020-07-31 17:05 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 68/76] fpu: add api to handle alternative sNaN propagation frank.chang
2020-07-22 9:16 ` [RFC v2 69/76] target/riscv: rvv-0.9: floating-point min/max instructions frank.chang
2020-07-22 9:16 ` [RFC v2 70/76] softfloat: add fp16 and uint8/int8 interconvert functions frank.chang
2020-07-22 9:16 ` [RFC v2 71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert frank.chang
2020-07-31 17:10 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 72/76] target/riscv: rvv-0.9: narrowing " frank.chang
2020-07-31 17:18 ` Richard Henderson
2020-07-22 9:16 ` [RFC v2 73/76] fpu: fix float16 nan check frank.chang
2020-07-22 9:16 ` [RFC v2 74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map frank.chang
2020-07-22 9:16 ` [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64 frank.chang
2020-07-31 17:25 ` Richard Henderson
2020-08-03 11:31 ` Alex Bennée
2020-07-22 9:16 ` [RFC v2 76/76] target/riscv: gdb: support vector registers for rv32 frank.chang
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