* [PULL v2 00/69] MIPS patches for 2021-01-14
@ 2021-01-14 16:19 Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 29/69] target/mips/translate: Add declarations for generic code Philippe Mathieu-Daudé
` (17 more replies)
0 siblings, 18 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:19 UTC (permalink / raw)
Cc: Aleksandar Rikalo, qemu-devel, Aurelien Jarno,
Philippe Mathieu-Daudé
Resending the MIPS pull request from MIPS patches from last week
(2021-01-07) now than the "decodetree: Open files with encoding='utf-8'"
patch got merged (commit 4cacecaaa2b).
Pre-existing checkpatch warnings in patch 23
(target/mips: Move common helpers from helper.c to cpu.c):
ERROR: space prohibited after that '&' (ctx:WxW)
#52: FILE: target/mips/cpu.c:53:
+ cu = (v >> CP0St_CU0) & 0xf;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#53: FILE: target/mips/cpu.c:54:
+ mx = (v >> CP0St_MX) & 0x1;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#54: FILE: target/mips/cpu.c:55:
+ ksu = (v >> CP0St_KSU) & 0x3;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#81: FILE: target/mips/cpu.c:82:
+ uint32_t ksux = (1 << CP0St_KX) & val;
^
ERROR: space prohibited after that '&' (ctx:WxW)
#89: FILE: target/mips/cpu.c:90:
+ mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val);
^
ERROR: space prohibited after that '&' (ctx:WxW)
#116: FILE: target/mips/cpu.c:117:
+ mask &= ~((1 << CP0Ca_WP) & val);
^
ERROR: space prohibited after that '&' (ctx:WxW)
#121: FILE: target/mips/cpu.c:122:
+ if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
^
ERROR: space prohibited after that '&' (ctx:WxW)
#131: FILE: target/mips/cpu.c:132:
+ if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
^
total: 8 errors, 0 warnings, 433 lines checked
The following changes since commit 7c79721606be11b5bc556449e5bcbc331ef6867d:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210113' into staging (2021-01-14 09:54:29 +0000)
are available in the Git repository at:
https://gitlab.com/philmd/qemu.git tags/mips-20210114
for you to fetch changes up to cd669e20516fad3d8154629f67d4b6caede9b381:
docs/system: Remove deprecated 'fulong2e' machine alias (2021-01-14 17:13:54 +0100)
----------------------------------------------------------------
MIPS patches queue
- Simplify CPU/ISA definitions
- Various maintenance code movements in translate.c
- Convert part of the MSA ASE instructions to decodetree
- Convert some instructions removed from Release 6 to decodetree
- Remove deprecated 'fulong2e' machine alias
----------------------------------------------------------------
Jiaxun Yang (1):
target/mips/addr: Add translation helpers for KSEG1
Philippe Mathieu-Daudé (68):
target/mips: Add CP0 Config0 register definitions for MIPS3 ISA
target/mips: Replace CP0_Config0 magic values by proper definitions
target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment
target/mips/mips-defs: Reorder CPU_MIPS5 definition
target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit()
hw/mips/boston: Check 64-bit support with cpu_type_is_64bit()
target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1
target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2
target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3
target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5
target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6
target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1
target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2
target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3
target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5
target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6
target/mips: Inline cpu_state_reset() in mips_cpu_reset()
target/mips: Extract FPU helpers to 'fpu_helper.h'
target/mips: Add !CONFIG_USER_ONLY comment after #endif
target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs
target/mips: Move common helpers from helper.c to cpu.c
target/mips: Rename helper.c as tlb_helper.c
target/mips: Fix code style for checkpatch.pl
target/mips: Move mmu_init() functions to tlb_helper.c
target/mips: Rename translate_init.c as cpu-defs.c
target/mips/translate: Extract DisasContext structure
target/mips/translate: Add declarations for generic code
target/mips: Replace gen_exception_err(err=0) by gen_exception_end()
target/mips: Replace gen_exception_end(EXCP_RI) by
gen_rsvd_instruction
target/mips: Declare generic FPU / Coprocessor functions in
translate.h
target/mips: Extract FPU specific definitions to translate.h
target/mips: Only build TCG code when CONFIG_TCG is set
target/mips/translate: Extract decode_opc_legacy() from decode_opc()
target/mips/translate: Expose check_mips_64() to 32-bit mode
target/mips: Introduce ase_msa_available() helper
target/mips: Simplify msa_reset()
target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA
target/mips: Simplify MSA TCG logic
target/mips: Remove now unused ASE_MSA definition
target/mips: Alias MSA vector registers on FPU scalar registers
target/mips: Extract msa_translate_init() from mips_tcg_init()
target/mips: Remove CPUMIPSState* argument from gen_msa*() methods
target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()
target/mips: Move msa_reset() to msa_helper.c
target/mips: Extract MSA helpers from op_helper.c
target/mips: Extract MSA helper definitions
target/mips: Declare gen_msa/_branch() in 'translate.h'
target/mips: Extract MSA translation routines
target/mips: Pass TCGCond argument to MSA gen_check_zero_element()
target/mips: Introduce decode tree bindings for MSA ASE
target/mips: Use decode_ase_msa() generated from decodetree
target/mips: Extract LSA/DLSA translation generators
target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes
target/mips: Introduce decodetree helpers for Release6 LSA/DLSA
opcodes
target/mips: Remove now unreachable LSA/DLSA opcodes code
target/mips: Convert Rel6 Special2 opcode to decodetree
target/mips: Convert Rel6 COP1X opcode to decodetree
target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree
target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree
target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree
target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
target/mips: Convert Rel6 LLD/SCD opcodes to decodetree
target/mips: Convert Rel6 LL/SC opcodes to decodetree
target/mips: Remove CPU_R5900 definition
target/mips: Remove CPU_NANOMIPS32 definition
target/mips: Remove vendor specific CPU definitions
docs/system: Remove deprecated 'fulong2e' machine alias
docs/system/deprecated.rst | 5 -
docs/system/removed-features.rst | 5 +
target/mips/cpu.h | 23 +-
target/mips/fpu_helper.h | 59 +
target/mips/helper.h | 436 +-
target/mips/internal.h | 64 +-
target/mips/mips-defs.h | 56 +-
target/mips/translate.h | 177 +
target/mips/msa_helper.h.inc | 443 ++
target/mips/mips32r6.decode | 36 +
target/mips/mips64r6.decode | 27 +
target/mips/msa32.decode | 29 +
target/mips/msa64.decode | 17 +
hw/mips/boston.c | 6 +-
hw/mips/fuloong2e.c | 1 -
linux-user/mips/cpu_loop.c | 7 +-
target/mips/addr.c | 10 +
target/mips/cp0_helper.c | 18 +-
target/mips/cp0_timer.c | 4 +-
target/mips/cpu.c | 255 +-
target/mips/fpu_helper.c | 5 +-
target/mips/gdbstub.c | 1 +
target/mips/kvm.c | 13 +-
target/mips/machine.c | 1 +
target/mips/msa_helper.c | 430 ++
target/mips/msa_translate.c | 2286 ++++++++++
target/mips/op_helper.c | 396 +-
target/mips/rel6_translate.c | 44 +
target/mips/{helper.c => tlb_helper.c} | 266 +-
target/mips/translate.c | 3860 ++++-------------
target/mips/translate_addr_const.c | 61 +
.../{translate_init.c.inc => cpu-defs.c.inc} | 128 +-
target/mips/meson.build | 21 +-
33 files changed, 4757 insertions(+), 4433 deletions(-)
create mode 100644 target/mips/fpu_helper.h
create mode 100644 target/mips/translate.h
create mode 100644 target/mips/msa_helper.h.inc
create mode 100644 target/mips/mips32r6.decode
create mode 100644 target/mips/mips64r6.decode
create mode 100644 target/mips/msa32.decode
create mode 100644 target/mips/msa64.decode
create mode 100644 target/mips/msa_translate.c
create mode 100644 target/mips/rel6_translate.c
rename target/mips/{helper.c => tlb_helper.c} (87%)
create mode 100644 target/mips/translate_addr_const.c
rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (92%)
--
2.26.2
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PULL v2 29/69] target/mips/translate: Add declarations for generic code
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 30/69] target/mips: Replace gen_exception_err(err=0) by gen_exception_end() Philippe Mathieu-Daudé
` (16 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
Some CPU translation functions / registers / macros and
definitions can be used by ISA / ASE / extensions out of
the big translate.c file. Declare them in "translate.h".
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201207235539.4070364-3-f4bug@amsat.org>
---
target/mips/translate.h | 43 ++++++++++++++++++++++++++++++++++
target/mips/translate.c | 52 +++++++++++------------------------------
2 files changed, 57 insertions(+), 38 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index fcda1a99001..3d640912f12 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -10,6 +10,8 @@
#include "exec/translator.h"
+#define MIPS_DEBUG_DISAS 0
+
typedef struct DisasContext {
DisasContextBase base;
target_ulong saved_pc;
@@ -47,4 +49,45 @@ typedef struct DisasContext {
int gi;
} DisasContext;
+/* MIPS major opcodes */
+#define MASK_OP_MAJOR(op) (op & (0x3F << 26))
+
+void generate_exception(DisasContext *ctx, int excp);
+void generate_exception_err(DisasContext *ctx, int excp, int err);
+void generate_exception_end(DisasContext *ctx, int excp);
+
+void check_insn(DisasContext *ctx, uint64_t flags);
+#ifdef TARGET_MIPS64
+void check_mips_64(DisasContext *ctx);
+#endif
+
+void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
+void gen_move_low32(TCGv ret, TCGv_i64 arg);
+void gen_move_high32(TCGv ret, TCGv_i64 arg);
+void gen_load_gpr(TCGv t, int reg);
+void gen_store_gpr(TCGv t, int reg);
+
+void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
+
+extern TCGv cpu_gpr[32], cpu_PC;
+extern TCGv bcond;
+
+#define LOG_DISAS(...) \
+ do { \
+ if (MIPS_DEBUG_DISAS) { \
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
+ } \
+ } while (0)
+
+#define MIPS_INVAL(op) \
+ do { \
+ if (MIPS_DEBUG_DISAS) { \
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, \
+ TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
+ ctx->base.pc_next, ctx->opcode, op, \
+ ctx->opcode >> 26, ctx->opcode & 0x3F, \
+ ((ctx->opcode >> 16) & 0x1F)); \
+ } \
+ } while (0)
+
#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9e824e12d44..72cbf604ac3 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -38,11 +38,6 @@
#include "fpu_helper.h"
#include "translate.h"
-#define MIPS_DEBUG_DISAS 0
-
-/* MIPS major opcodes */
-#define MASK_OP_MAJOR(op) (op & (0x3F << 26))
-
enum {
/* indirect opcode tables */
OPC_SPECIAL = (0x00 << 26),
@@ -2491,9 +2486,10 @@ enum {
};
/* global register indices */
-static TCGv cpu_gpr[32], cpu_PC;
+TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
-static TCGv cpu_dspctrl, btarget, bcond;
+static TCGv cpu_dspctrl, btarget;
+TCGv bcond;
static TCGv cpu_lladdr, cpu_llval;
static TCGv_i32 hflags;
static TCGv_i32 fpu_fcr0, fpu_fcr31;
@@ -2606,26 +2602,8 @@ static const char * const mxuregnames[] = {
};
#endif
-#define LOG_DISAS(...) \
- do { \
- if (MIPS_DEBUG_DISAS) { \
- qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \
- } \
- } while (0)
-
-#define MIPS_INVAL(op) \
- do { \
- if (MIPS_DEBUG_DISAS) { \
- qemu_log_mask(CPU_LOG_TB_IN_ASM, \
- TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
- ctx->base.pc_next, ctx->opcode, op, \
- ctx->opcode >> 26, ctx->opcode & 0x3F, \
- ((ctx->opcode >> 16) & 0x1F)); \
- } \
- } while (0)
-
/* General purpose registers moves. */
-static inline void gen_load_gpr(TCGv t, int reg)
+void gen_load_gpr(TCGv t, int reg)
{
if (reg == 0) {
tcg_gen_movi_tl(t, 0);
@@ -2634,7 +2612,7 @@ static inline void gen_load_gpr(TCGv t, int reg)
}
}
-static inline void gen_store_gpr(TCGv t, int reg)
+void gen_store_gpr(TCGv t, int reg)
{
if (reg != 0) {
tcg_gen_mov_tl(cpu_gpr[reg], t);
@@ -2763,7 +2741,7 @@ static inline void restore_cpu_state(CPUMIPSState *env, DisasContext *ctx)
}
}
-static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
+void generate_exception_err(DisasContext *ctx, int excp, int err)
{
TCGv_i32 texcp = tcg_const_i32(excp);
TCGv_i32 terr = tcg_const_i32(err);
@@ -2774,12 +2752,12 @@ static inline void generate_exception_err(DisasContext *ctx, int excp, int err)
ctx->base.is_jmp = DISAS_NORETURN;
}
-static inline void generate_exception(DisasContext *ctx, int excp)
+void generate_exception(DisasContext *ctx, int excp)
{
gen_helper_0e0i(raise_exception, excp);
}
-static inline void generate_exception_end(DisasContext *ctx, int excp)
+void generate_exception_end(DisasContext *ctx, int excp)
{
generate_exception_err(ctx, excp, 0);
}
@@ -2859,8 +2837,7 @@ static inline int get_fp_bit(int cc)
}
/* Addresses computation */
-static inline void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0,
- TCGv arg1)
+void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1)
{
tcg_gen_add_tl(ret, arg0, arg1);
@@ -2898,7 +2875,7 @@ static target_long addr_add(DisasContext *ctx, target_long base,
}
/* Sign-extract the low 32-bits to a target_long. */
-static inline void gen_move_low32(TCGv ret, TCGv_i64 arg)
+void gen_move_low32(TCGv ret, TCGv_i64 arg)
{
#if defined(TARGET_MIPS64)
tcg_gen_ext32s_i64(ret, arg);
@@ -2908,7 +2885,7 @@ static inline void gen_move_low32(TCGv ret, TCGv_i64 arg)
}
/* Sign-extract the high 32-bits to a target_long. */
-static inline void gen_move_high32(TCGv ret, TCGv_i64 arg)
+void gen_move_high32(TCGv ret, TCGv_i64 arg)
{
#if defined(TARGET_MIPS64)
tcg_gen_sari_i64(ret, arg, 32);
@@ -3013,7 +2990,7 @@ static inline void check_dsp_r3(DisasContext *ctx)
* This code generates a "reserved instruction" exception if the
* CPU does not support the instruction set corresponding to flags.
*/
-static inline void check_insn(DisasContext *ctx, uint64_t flags)
+void check_insn(DisasContext *ctx, uint64_t flags)
{
if (unlikely(!(ctx->insn_flags & flags))) {
generate_exception_end(ctx, EXCP_RI);
@@ -3064,7 +3041,7 @@ static inline void check_ps(DisasContext *ctx)
* This code generates a "reserved instruction" exception if 64-bit
* instructions are not enabled.
*/
-static inline void check_mips_64(DisasContext *ctx)
+void check_mips_64(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
generate_exception_end(ctx, EXCP_RI);
@@ -3390,8 +3367,7 @@ OP_LD_ATOMIC(lld, ld64);
#endif
#undef OP_LD_ATOMIC
-static void gen_base_offset_addr(DisasContext *ctx, TCGv addr,
- int base, int offset)
+void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset)
{
if (base == 0) {
tcg_gen_movi_tl(addr, offset);
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 30/69] target/mips: Replace gen_exception_err(err=0) by gen_exception_end()
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 29/69] target/mips/translate: Add declarations for generic code Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 31/69] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction Philippe Mathieu-Daudé
` (15 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
generate_exception_err(err=0) is simply generate_exception_end().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-11-f4bug@amsat.org>
---
target/mips/translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 72cbf604ac3..fa11c8ffe0c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2897,7 +2897,7 @@ void gen_move_high32(TCGv ret, TCGv_i64 arg)
static inline void check_cp0_enabled(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
- generate_exception_err(ctx, EXCP_CpU, 0);
+ generate_exception_end(ctx, EXCP_CpU);
}
}
@@ -3103,10 +3103,10 @@ static inline void check_mt(DisasContext *ctx)
static inline void check_cp0_mt(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
- generate_exception_err(ctx, EXCP_CpU, 0);
+ generate_exception_end(ctx, EXCP_CpU);
} else {
if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
- generate_exception_err(ctx, EXCP_RI, 0);
+ generate_exception_end(ctx, EXCP_RI);
}
}
}
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 31/69] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 29/69] target/mips/translate: Add declarations for generic code Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 30/69] target/mips: Replace gen_exception_err(err=0) by gen_exception_end() Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 32/69] target/mips: Declare generic FPU / Coprocessor functions in translate.h Philippe Mathieu-Daudé
` (14 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
gen_reserved_instruction() is easier to read than
generate_exception_end(ctx, EXCP_RI), replace it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-12-f4bug@amsat.org>
---
target/mips/translate.h | 1 +
target/mips/translate.c | 729 ++++++++++++++++++++--------------------
2 files changed, 368 insertions(+), 362 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 3d640912f12..98cadffe4e5 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -55,6 +55,7 @@ typedef struct DisasContext {
void generate_exception(DisasContext *ctx, int excp);
void generate_exception_err(DisasContext *ctx, int excp, int err);
void generate_exception_end(DisasContext *ctx, int excp);
+void gen_reserved_instruction(DisasContext *ctx);
void check_insn(DisasContext *ctx, uint64_t flags);
#ifdef TARGET_MIPS64
diff --git a/target/mips/translate.c b/target/mips/translate.c
index fa11c8ffe0c..d7767215050 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2762,6 +2762,11 @@ void generate_exception_end(DisasContext *ctx, int excp)
generate_exception_err(ctx, excp, 0);
}
+void gen_reserved_instruction(DisasContext *ctx)
+{
+ generate_exception_end(ctx, EXCP_RI);
+}
+
/* Floating point register moves. */
static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
{
@@ -2916,7 +2921,7 @@ static inline void check_cp1_enabled(DisasContext *ctx)
static inline void check_cop1x(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -2927,7 +2932,7 @@ static inline void check_cop1x(DisasContext *ctx)
static inline void check_cp1_64bitmode(DisasContext *ctx)
{
if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -2945,7 +2950,7 @@ static inline void check_cp1_64bitmode(DisasContext *ctx)
static inline void check_cp1_registers(DisasContext *ctx, int regs)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -2959,7 +2964,7 @@ static inline void check_dsp(DisasContext *ctx)
if (ctx->insn_flags & ASE_DSP) {
generate_exception_end(ctx, EXCP_DSPDIS);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
}
@@ -2970,7 +2975,7 @@ static inline void check_dsp_r2(DisasContext *ctx)
if (ctx->insn_flags & ASE_DSP) {
generate_exception_end(ctx, EXCP_DSPDIS);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
}
@@ -2981,7 +2986,7 @@ static inline void check_dsp_r3(DisasContext *ctx)
if (ctx->insn_flags & ASE_DSP) {
generate_exception_end(ctx, EXCP_DSPDIS);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
}
@@ -2993,7 +2998,7 @@ static inline void check_dsp_r3(DisasContext *ctx)
void check_insn(DisasContext *ctx, uint64_t flags)
{
if (unlikely(!(ctx->insn_flags & flags))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -3005,7 +3010,7 @@ void check_insn(DisasContext *ctx, uint64_t flags)
static inline void check_insn_opc_removed(DisasContext *ctx, uint64_t flags)
{
if (unlikely(ctx->insn_flags & flags)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -3044,7 +3049,7 @@ static inline void check_ps(DisasContext *ctx)
void check_mips_64(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
#endif
@@ -3065,7 +3070,7 @@ static inline void check_mvh(DisasContext *ctx)
static inline void check_xnp(DisasContext *ctx)
{
if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -3077,7 +3082,7 @@ static inline void check_xnp(DisasContext *ctx)
static inline void check_pw(DisasContext *ctx)
{
if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_PW)))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
#endif
@@ -3089,7 +3094,7 @@ static inline void check_pw(DisasContext *ctx)
static inline void check_mt(DisasContext *ctx)
{
if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -3106,7 +3111,7 @@ static inline void check_cp0_mt(DisasContext *ctx)
generate_exception_end(ctx, EXCP_CpU);
} else {
if (unlikely(!(ctx->CP0_Config3 & (1 << CP0C3_MT)))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
}
@@ -3119,7 +3124,7 @@ static inline void check_cp0_mt(DisasContext *ctx)
static inline void check_nms(DisasContext *ctx)
{
if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_NMS))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -3136,7 +3141,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
!(ctx->CP0_Config2 & (1 << CP0C2_SL)) &&
!(ctx->CP0_Config2 & (1 << CP0C2_TL)) &&
!(ctx->CP0_Config5 & (1 << CP0C5_L2C)))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -3147,7 +3152,7 @@ static inline void check_nms_dl_il_sl_tl_l2c(DisasContext *ctx)
static inline void check_eva(DisasContext *ctx)
{
if (unlikely(!(ctx->CP0_Config5 & (1 << CP0C5_EVA)))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
}
@@ -3812,7 +3817,7 @@ static void gen_flt_ldst(DisasContext *ctx, uint32_t opc, int ft,
break;
default:
MIPS_INVAL("flt_ldst");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -4461,7 +4466,7 @@ static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
break;
default:
MIPS_INVAL("mfthilo1 TX79");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -4596,7 +4601,7 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc,
#endif
default:
MIPS_INVAL("OPC_PCREL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -4807,7 +4812,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
#endif
default:
MIPS_INVAL("r6 mul/div");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
out:
@@ -4865,7 +4870,7 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
break;
default:
MIPS_INVAL("div1 TX79");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
out:
@@ -5058,7 +5063,7 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("mul/div");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
out:
@@ -5189,7 +5194,7 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("mul/madd TXx9");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -5252,7 +5257,7 @@ static void gen_mul_vr54xx(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("mul vr54xx");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
gen_store_gpr(t0, rd);
@@ -5878,7 +5883,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt)
break;
default:
MIPS_INVAL("loongson_cp2");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -6067,7 +6072,7 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
#endif
default:
MIPS_INVAL("loongson_gsshfl");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -6115,13 +6120,13 @@ static void gen_loongson_lswc2(DisasContext *ctx, int rt,
#endif
default:
MIPS_INVAL("loongson_gsshfs");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
default:
MIPS_INVAL("loongson_gslsq");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
tcg_temp_free(t0);
@@ -6170,7 +6175,7 @@ static void gen_loongson_lsdc2(DisasContext *ctx, int rt,
break;
default:
MIPS_INVAL("loongson_lsdc2");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
break;
}
@@ -6426,7 +6431,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
TARGET_FMT_lx "\n", ctx->base.pc_next);
#endif
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -6489,14 +6494,14 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
* others are reserved.
*/
MIPS_INVAL("jump hint");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
gen_load_gpr(btarget, rs);
break;
default:
MIPS_INVAL("branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
if (bcond_compute == 0) {
@@ -6561,7 +6566,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
} else {
@@ -6632,7 +6637,7 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("conditional branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
}
@@ -6709,14 +6714,14 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
* others are reserved.
*/
MIPS_INVAL("jump hint");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
gen_load_gpr(btarget, rs);
break;
default:
MIPS_INVAL("branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
if (bcond_compute == 0) {
@@ -6749,7 +6754,7 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
} else {
@@ -6772,7 +6777,7 @@ static void gen_compute_branch_nm(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("conditional branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
}
@@ -6852,7 +6857,7 @@ static void gen_bitops(DisasContext *ctx, uint32_t opc, int rt,
default:
fail:
MIPS_INVAL("bitops");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
tcg_temp_free(t0);
tcg_temp_free(t1);
return;
@@ -6930,7 +6935,7 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
#endif
default:
MIPS_INVAL("bsfhl");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
tcg_temp_free(t0);
return;
}
@@ -10584,7 +10589,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
die:
tcg_temp_free(t0);
LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
@@ -10794,7 +10799,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
die:
tcg_temp_free(t0);
LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
@@ -10954,7 +10959,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
}
if (!(ctx->hflags & MIPS_HFLAG_DM)) {
MIPS_INVAL(opn);
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
gen_helper_deret(cpu_env);
ctx->base.is_jmp = DISAS_EXIT;
@@ -10977,7 +10982,7 @@ static void gen_cp0(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
default:
die:
MIPS_INVAL(opn);
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
(void)opn; /* avoid a compiler warning */
@@ -10992,7 +10997,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
TCGv_i32 t0 = tcg_temp_new_i32();
if ((ctx->insn_flags & ISA_MIPS_R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -11083,7 +11088,7 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op,
break;
default:
MIPS_INVAL("cp1 cond branch");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
ctx->btarget = btarget;
@@ -11105,7 +11110,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
"\n", ctx->base.pc_next);
#endif
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -11125,7 +11130,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
break;
default:
MIPS_INVAL("cp1 cond branch");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -11433,7 +11438,7 @@ static void gen_cp1(DisasContext *ctx, uint32_t opc, int rt, int fs)
break;
default:
MIPS_INVAL("cp1 move");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -11570,7 +11575,7 @@ static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft,
break;
default:
MIPS_INVAL("gen_sel_s");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -11607,7 +11612,7 @@ static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft,
break;
default:
MIPS_INVAL("gen_sel_d");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -13041,7 +13046,7 @@ static void gen_farith(DisasContext *ctx, enum fopcode op1,
break;
default:
MIPS_INVAL("farith");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
}
@@ -13380,7 +13385,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("flt3_arith");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
}
@@ -13455,13 +13460,13 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel)
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
gen_store_gpr(t0, rt);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
#endif
default: /* Invalid */
MIPS_INVAL("rdhwr");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
tcg_temp_free(t0);
@@ -13560,7 +13565,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
"\n", ctx->base.pc_next);
#endif
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -13622,7 +13627,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("Compact branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -13643,7 +13648,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("Compact branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -13766,7 +13771,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("Compact conditional branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -13940,7 +13945,7 @@ static void gen_mips16_save(DisasContext *ctx,
args = 4;
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -14036,7 +14041,7 @@ static void gen_mips16_save(DisasContext *ctx,
astatic = 4;
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -14142,7 +14147,7 @@ static void gen_mips16_restore(DisasContext *ctx,
astatic = 4;
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -14173,7 +14178,7 @@ static void gen_addiupc(DisasContext *ctx, int rx, int imm,
TCGv t0;
if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -14231,7 +14236,7 @@ static void decode_i64_mips16(DisasContext *ctx,
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
offset = extended ? offset : offset << 3;
gen_ld(ctx, OPC_LDPC, ry, 0, offset);
@@ -14308,7 +14313,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
check_mips_64(ctx);
gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa);
#else
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
#endif
break;
case 0x2:
@@ -14336,7 +14341,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
check_mips_64(ctx);
gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm);
#else
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
#endif
} else {
gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm);
@@ -14388,7 +14393,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -14451,7 +14456,7 @@ static int decode_extended_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
break;
#endif
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -14540,7 +14545,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
check_mips_64(ctx);
gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa);
#else
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
#endif
break;
case 0x2:
@@ -14568,7 +14573,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
check_mips_64(ctx);
gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm);
#else
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
#endif
} else {
gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm);
@@ -14652,7 +14657,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
gen_arith(ctx, OPC_ADDU, ry, reg32, 0);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -14742,7 +14747,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
break;
#endif
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto done;
}
@@ -14859,7 +14864,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
break;
#endif
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -14923,7 +14928,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
break;
#endif
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -14938,7 +14943,7 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
break;
#endif
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -15636,7 +15641,7 @@ static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,
TCGv_i32 t2;
if (ctx->hflags & MIPS_HFLAG_BMASK) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -15789,7 +15794,7 @@ static void gen_pool16c_insn(DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -15934,7 +15939,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
TCGv t0, t1;
if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -15946,7 +15951,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
switch (opc) {
case LWP:
if (rd == base) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
@@ -15967,7 +15972,7 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
#ifdef TARGET_MIPS64
case LDP:
if (rd == base) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ);
@@ -16312,7 +16317,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
} else {
check_insn(ctx, ISA_MIPS_R1);
if (ctx->hflags & MIPS_HFLAG_SBRI) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
generate_exception_end(ctx, EXCP_DBp);
}
@@ -16362,7 +16367,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
default:
pool32axf_invalid:
MIPS_INVAL("pool32axf");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -16631,7 +16636,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs)
break;
default:
MIPS_INVAL("pool32fxf");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -16835,12 +16840,12 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case SIGRIE:
check_insn(ctx, ISA_MIPS_R6);
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
pool32a_invalid:
MIPS_INVAL("pool32a");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -16882,7 +16887,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("pool32b");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -17362,7 +17367,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
default:
pool32f_invalid:
MIPS_INVAL("pool32f");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
} else {
@@ -17524,7 +17529,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
/* Fall through */
default:
MIPS_INVAL("pool32i");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -17607,7 +17612,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
case LD_EVA:
if (!ctx->eva) {
MIPS_INVAL("pool32c ld-eva");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
check_cp0_enabled(ctx);
@@ -17646,7 +17651,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
case ST_EVA:
if (!ctx->eva) {
MIPS_INVAL("pool32c st-eva");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
check_cp0_enabled(ctx);
@@ -17698,7 +17703,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("pool32c");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -17990,7 +17995,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
gen_st(ctx, mips32_op, rt, rs, imm);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -18021,7 +18026,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx)
case 7:
/* LB32, LH32, LWC132, LDC132, LW32 */
if (ctx->hflags & MIPS_HFLAG_BDS16) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return 2;
}
break;
@@ -18032,7 +18037,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx)
case 3:
/* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */
if (ctx->hflags & MIPS_HFLAG_BDS32) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return 2;
}
break;
@@ -18105,7 +18110,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx)
case POOL16F:
check_insn_opc_removed(ctx, ISA_MIPS_R6);
if (ctx->opcode & 1) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
/* MOVEP */
int enc_dest = uMIPS_RD(ctx->opcode);
@@ -18243,7 +18248,7 @@ static int decode_micromips_opc(CPUMIPSState *env, DisasContext *ctx)
case RES_29:
case RES_31:
case RES_39:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
decode_micromips32_opc(env, ctx);
@@ -19501,7 +19506,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
gen_helper_dvpe(t0, cpu_env);
gen_store_gpr(t0, rt);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
case 1:
@@ -19516,7 +19521,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
gen_helper_evpe(t0, cpu_env);
gen_store_gpr(t0, rt);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
}
@@ -19566,7 +19571,7 @@ static void gen_pool32a0_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
break;
#endif
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -19607,7 +19612,7 @@ static void gen_pool32axf_1_5_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_helper_maq_sa_w_phl(t0, v1_t, v0_t, cpu_env);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -19658,7 +19663,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_helper_shilo(t0, v0_t, cpu_env);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -19732,7 +19737,7 @@ static void gen_pool32axf_1_nanomips_insn(DisasContext *ctx, uint32_t opc,
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -19770,7 +19775,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_dpsq_s_w_ph(t0, v1, v0, cpu_env);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -19793,7 +19798,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_dpsq_sa_l_w(t0, v0, v1, cpu_env);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -19820,7 +19825,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_mulsa_w_ph(t0, v0, v1, cpu_env);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -19847,12 +19852,12 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_mulsaq_s_w_ph(t0, v1, v0, cpu_env);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -19996,7 +20001,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_store_gpr(t0, ret);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -20089,7 +20094,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -20232,7 +20237,7 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_bshfl(ctx, OPC_WSBH, ret, rs);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -20287,7 +20292,7 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
tcg_temp_free(t0);
@@ -20384,7 +20389,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
break;
#endif
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -20395,7 +20400,7 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -20428,7 +20433,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
case NM_BBNEZC:
check_nms(ctx);
if (imm >= 32 && !(ctx->hflags & MIPS_HFLAG_64)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
} else if (rt == 0 && opc == NM_BBEQZC) {
/* Unconditional branch */
@@ -20478,7 +20483,7 @@ static void gen_compute_imm_branch(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("Immediate Value Compact branch");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -20591,7 +20596,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("Compact branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -20603,7 +20608,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("Compact branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
} else {
@@ -20664,7 +20669,7 @@ static void gen_compute_compact_branch_nm(DisasContext *ctx, uint32_t opc,
break;
default:
MIPS_INVAL("Compact conditional branch/jump");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -20708,7 +20713,7 @@ static void gen_compute_branch_cp1_nm(DisasContext *ctx, uint32_t op,
break;
default:
MIPS_INVAL("cp1 cond branch");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
goto out;
}
@@ -20838,7 +20843,7 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -20855,7 +20860,7 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)
rd = extract32(ctx->opcode, 11, 5);
if (!(ctx->CP0_Config1 & (1 << CP0C1_FP))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
check_cp1_enabled(ctx);
@@ -20929,7 +20934,7 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)
gen_farith(ctx, OPC_MSUBF_D, rt, rs, rd, 0);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -21118,7 +21123,7 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)
gen_farith(ctx, OPC_CVT_S_L, -1, rs, rt, 0);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -21135,12 +21140,12 @@ static void gen_pool32f_nanomips_insn(DisasContext *ctx)
gen_r6_cmp_d(ctx, extract32(ctx->opcode, 6, 5), rt, rs, rd);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -21666,7 +21671,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
gen_store_gpr(v1_t, rt);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -21688,7 +21693,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -21716,13 +21721,13 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
switch (extract32(ctx->opcode, 19, 2)) {
case NM_SIGRIE:
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case NM_P_SYSCALL:
if ((extract32(ctx->opcode, 18, 1)) == NM_SYSCALL) {
generate_exception_end(ctx, EXCP_SYSCALL);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
case NM_BREAK:
@@ -21733,7 +21738,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_helper_do_semihosting(cpu_env);
} else {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
generate_exception_end(ctx, EXCP_DBp);
}
@@ -21791,12 +21796,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_pool32axf_nanomips_insn(env, ctx);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -21815,7 +21820,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_st(ctx, OPC_SW, rt, 28, extract32(ctx->opcode, 2, 19) << 2);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -21886,7 +21891,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
return 6;
@@ -21921,12 +21926,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
case NM_P_SR_F:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22014,7 +22019,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
extract32(ctx->opcode, 6, 5));
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22027,12 +22032,12 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
extract32(ctx->opcode, 6, 5));
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22100,7 +22105,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_st(ctx, OPC_SH, rt, 28, u);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22122,7 +22127,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -22182,7 +22187,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_cop1_ldst(ctx, OPC_SDC1, rt, rs, u);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -22245,7 +22250,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22385,7 +22390,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22405,7 +22410,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
true);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22456,7 +22461,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -22500,7 +22505,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_compute_nanomips_pbalrsc_branch(ctx, rs, rt);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22535,7 +22540,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22584,7 +22589,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -22600,7 +22605,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
return 4;
@@ -22639,7 +22644,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
if (extract32(ctx->opcode, 2, 1) == 0) {
generate_exception_end(ctx, EXCP_SYSCALL);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
case NM_BREAK16:
@@ -22650,14 +22655,14 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
gen_helper_do_semihosting(cpu_env);
} else {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
generate_exception_end(ctx, EXCP_DBp);
}
}
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -22696,7 +22701,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
gen_arith_imm(ctx, OPC_ADDIU, rt, 29, imm);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22745,7 +22750,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
gen_r6_muldiv(ctx, R6_OPC_MUL, rt, rs, rt);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22781,7 +22786,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
gen_ld(ctx, OPC_LBU, rt, rs, offset);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -22800,7 +22805,7 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
gen_ld(ctx, OPC_LHU, rt, rs, offset);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -23579,7 +23584,7 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
break;
default: /* Invalid */
MIPS_INVAL("MASK SHLL.QB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -23694,7 +23699,7 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
break;
default: /* Invalid */
MIPS_INVAL("MASK SHLL.OB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -24385,7 +24390,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx,
break;
default: /* Invalid */
MIPS_INVAL("MASK APPEND");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -24419,7 +24424,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx,
break;
default: /* Invalid */
MIPS_INVAL("MASK DAPPEND");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -24688,7 +24693,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("special_r6 muldiv");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -24705,7 +24710,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
*/
gen_cl(ctx, op1, rd, rs);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
case R6_OPC_SDBBP:
@@ -24713,7 +24718,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
gen_helper_do_semihosting(cpu_env);
} else {
if (ctx->hflags & MIPS_HFLAG_SBRI) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
generate_exception_end(ctx, EXCP_DBp);
}
@@ -24734,7 +24739,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
case OPC_DMULT:
@@ -24757,14 +24762,14 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("special_r6 muldiv");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
#endif
default: /* Invalid */
MIPS_INVAL("special_r6");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -24811,7 +24816,7 @@ static void decode_opc_special_tx79(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("special_tx79");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -24882,16 +24887,16 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_SPIM:
#ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("SPIM");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
#else
/* Implemented as RI exception for now. */
MIPS_INVAL("spim (unofficial)");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
#endif
break;
default: /* Invalid */
MIPS_INVAL("special_legacy");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -24913,7 +24918,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
rs == 0 && rt == 0) { /* PAUSE */
if ((ctx->insn_flags & ISA_MIPS_R6) &&
(ctx->hflags & MIPS_HFLAG_BMASK)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -24933,7 +24938,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
gen_shift_imm(ctx, op1, rd, rt, sa);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -24959,7 +24964,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
gen_shift(ctx, op1, rd, rs, rt);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -24993,7 +24998,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
/* Pmon entry point, also R4010 selsl */
#ifdef MIPS_STRICT_STANDARD
MIPS_INVAL("PMON / selsl");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
#else
gen_helper_0e0i(pmon, sa);
#endif
@@ -25034,7 +25039,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
gen_shift_imm(ctx, op1, rd, rt, sa);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -25052,7 +25057,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
gen_shift_imm(ctx, op1, rd, rt, sa);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -25084,7 +25089,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
gen_shift(ctx, op1, rd, rs, rt);
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -25149,7 +25154,7 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
rd = extract32(opcode, 11, 5);
if (unlikely(pd != 0)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else if (rd == 0) {
/* nop */
} else if (rt == 0) {
@@ -26356,16 +26361,16 @@ static void decode_opc_mxu__pool00(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_Q8SLT:
/* TODO: Implement emulation of Q8SLT instruction. */
MIPS_INVAL("OPC_MXU_Q8SLT");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8SLTU:
/* TODO: Implement emulation of Q8SLTU instruction. */
MIPS_INVAL("OPC_MXU_Q8SLTU");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26395,41 +26400,41 @@ static void decode_opc_mxu__pool01(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_S32SLT:
/* TODO: Implement emulation of S32SLT instruction. */
MIPS_INVAL("OPC_MXU_S32SLT");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16SLT:
/* TODO: Implement emulation of D16SLT instruction. */
MIPS_INVAL("OPC_MXU_D16SLT");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16AVG:
/* TODO: Implement emulation of D16AVG instruction. */
MIPS_INVAL("OPC_MXU_D16AVG");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16AVGR:
/* TODO: Implement emulation of D16AVGR instruction. */
MIPS_INVAL("OPC_MXU_D16AVGR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8AVG:
/* TODO: Implement emulation of Q8AVG instruction. */
MIPS_INVAL("OPC_MXU_Q8AVG");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8AVGR:
/* TODO: Implement emulation of Q8AVGR instruction. */
MIPS_INVAL("OPC_MXU_Q8AVGR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8ADD:
/* TODO: Implement emulation of Q8ADD instruction. */
MIPS_INVAL("OPC_MXU_Q8ADD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26452,26 +26457,26 @@ static void decode_opc_mxu__pool02(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_S32CPS:
/* TODO: Implement emulation of S32CPS instruction. */
MIPS_INVAL("OPC_MXU_S32CPS");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16CPS:
/* TODO: Implement emulation of D16CPS instruction. */
MIPS_INVAL("OPC_MXU_D16CPS");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8ABD:
/* TODO: Implement emulation of Q8ABD instruction. */
MIPS_INVAL("OPC_MXU_Q8ABD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16SAT:
/* TODO: Implement emulation of Q16SAT instruction. */
MIPS_INVAL("OPC_MXU_Q16SAT");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26501,16 +26506,16 @@ static void decode_opc_mxu__pool03(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_D16MULF:
/* TODO: Implement emulation of D16MULF instruction. */
MIPS_INVAL("OPC_MXU_D16MULF");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16MULE:
/* TODO: Implement emulation of D16MULE instruction. */
MIPS_INVAL("OPC_MXU_D16MULE");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26536,7 +26541,7 @@ static void decode_opc_mxu__pool04(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26559,16 +26564,16 @@ static void decode_opc_mxu__pool05(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_S32STD:
/* TODO: Implement emulation of S32STD instruction. */
MIPS_INVAL("OPC_MXU_S32STD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32STDR:
/* TODO: Implement emulation of S32STDR instruction. */
MIPS_INVAL("OPC_MXU_S32STDR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26591,16 +26596,16 @@ static void decode_opc_mxu__pool06(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_S32LDDV:
/* TODO: Implement emulation of S32LDDV instruction. */
MIPS_INVAL("OPC_MXU_S32LDDV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32LDDVR:
/* TODO: Implement emulation of S32LDDVR instruction. */
MIPS_INVAL("OPC_MXU_S32LDDVR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26623,16 +26628,16 @@ static void decode_opc_mxu__pool07(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_S32STDV:
/* TODO: Implement emulation of S32TDV instruction. */
MIPS_INVAL("OPC_MXU_S32TDV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32STDVR:
/* TODO: Implement emulation of S32TDVR instruction. */
MIPS_INVAL("OPC_MXU_S32TDVR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26655,16 +26660,16 @@ static void decode_opc_mxu__pool08(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_S32LDI:
/* TODO: Implement emulation of S32LDI instruction. */
MIPS_INVAL("OPC_MXU_S32LDI");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32LDIR:
/* TODO: Implement emulation of S32LDIR instruction. */
MIPS_INVAL("OPC_MXU_S32LDIR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26687,16 +26692,16 @@ static void decode_opc_mxu__pool09(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_S32SDI:
/* TODO: Implement emulation of S32SDI instruction. */
MIPS_INVAL("OPC_MXU_S32SDI");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32SDIR:
/* TODO: Implement emulation of S32SDIR instruction. */
MIPS_INVAL("OPC_MXU_S32SDIR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26719,16 +26724,16 @@ static void decode_opc_mxu__pool10(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_S32LDIV:
/* TODO: Implement emulation of S32LDIV instruction. */
MIPS_INVAL("OPC_MXU_S32LDIV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32LDIVR:
/* TODO: Implement emulation of S32LDIVR instruction. */
MIPS_INVAL("OPC_MXU_S32LDIVR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26751,16 +26756,16 @@ static void decode_opc_mxu__pool11(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_S32SDIV:
/* TODO: Implement emulation of S32SDIV instruction. */
MIPS_INVAL("OPC_MXU_S32SDIV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32SDIVR:
/* TODO: Implement emulation of S32SDIVR instruction. */
MIPS_INVAL("OPC_MXU_S32SDIVR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26783,21 +26788,21 @@ static void decode_opc_mxu__pool12(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_D32ACC:
/* TODO: Implement emulation of D32ACC instruction. */
MIPS_INVAL("OPC_MXU_D32ACC");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32ACCM:
/* TODO: Implement emulation of D32ACCM instruction. */
MIPS_INVAL("OPC_MXU_D32ACCM");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32ASUM:
/* TODO: Implement emulation of D32ASUM instruction. */
MIPS_INVAL("OPC_MXU_D32ASUM");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26820,21 +26825,21 @@ static void decode_opc_mxu__pool13(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_Q16ACC:
/* TODO: Implement emulation of Q16ACC instruction. */
MIPS_INVAL("OPC_MXU_Q16ACC");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16ACCM:
/* TODO: Implement emulation of Q16ACCM instruction. */
MIPS_INVAL("OPC_MXU_Q16ACCM");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16ASUM:
/* TODO: Implement emulation of Q16ASUM instruction. */
MIPS_INVAL("OPC_MXU_Q16ASUM");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26864,21 +26869,21 @@ static void decode_opc_mxu__pool14(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_Q8ADDE:
/* TODO: Implement emulation of Q8ADDE instruction. */
MIPS_INVAL("OPC_MXU_Q8ADDE");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D8SUM:
/* TODO: Implement emulation of D8SUM instruction. */
MIPS_INVAL("OPC_MXU_D8SUM");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D8SUMC:
/* TODO: Implement emulation of D8SUMC instruction. */
MIPS_INVAL("OPC_MXU_D8SUMC");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26908,26 +26913,26 @@ static void decode_opc_mxu__pool15(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_S32MUL:
/* TODO: Implement emulation of S32MUL instruction. */
MIPS_INVAL("OPC_MXU_S32MUL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32MULU:
/* TODO: Implement emulation of S32MULU instruction. */
MIPS_INVAL("OPC_MXU_S32MULU");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32EXTR:
/* TODO: Implement emulation of S32EXTR instruction. */
MIPS_INVAL("OPC_MXU_S32EXTR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32EXTRV:
/* TODO: Implement emulation of S32EXTRV instruction. */
MIPS_INVAL("OPC_MXU_S32EXTRV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -26975,12 +26980,12 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_D32SARW:
/* TODO: Implement emulation of D32SARW instruction. */
MIPS_INVAL("OPC_MXU_D32SARW");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32ALN:
/* TODO: Implement emulation of S32ALN instruction. */
MIPS_INVAL("OPC_MXU_S32ALN");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32ALNI:
gen_mxu_S32ALNI(ctx);
@@ -26988,7 +26993,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_S32LUI:
/* TODO: Implement emulation of S32LUI instruction. */
MIPS_INVAL("OPC_MXU_S32LUI");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32NOR:
gen_mxu_S32NOR(ctx);
@@ -27004,7 +27009,7 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27027,31 +27032,31 @@ static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_LXW:
/* TODO: Implement emulation of LXW instruction. */
MIPS_INVAL("OPC_MXU_LXW");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_LXH:
/* TODO: Implement emulation of LXH instruction. */
MIPS_INVAL("OPC_MXU_LXH");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_LXHU:
/* TODO: Implement emulation of LXHU instruction. */
MIPS_INVAL("OPC_MXU_LXHU");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_LXB:
/* TODO: Implement emulation of LXB instruction. */
MIPS_INVAL("OPC_MXU_LXB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_LXBU:
/* TODO: Implement emulation of LXBU instruction. */
MIPS_INVAL("OPC_MXU_LXBU");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27073,36 +27078,36 @@ static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_D32SLLV:
/* TODO: Implement emulation of D32SLLV instruction. */
MIPS_INVAL("OPC_MXU_D32SLLV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32SLRV:
/* TODO: Implement emulation of D32SLRV instruction. */
MIPS_INVAL("OPC_MXU_D32SLRV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32SARV:
/* TODO: Implement emulation of D32SARV instruction. */
MIPS_INVAL("OPC_MXU_D32SARV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16SLLV:
/* TODO: Implement emulation of Q16SLLV instruction. */
MIPS_INVAL("OPC_MXU_Q16SLLV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16SLRV:
/* TODO: Implement emulation of Q16SLRV instruction. */
MIPS_INVAL("OPC_MXU_Q16SLRV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16SARV:
/* TODO: Implement emulation of Q16SARV instruction. */
MIPS_INVAL("OPC_MXU_Q16SARV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27128,7 +27133,7 @@ static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27151,36 +27156,36 @@ static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_Q8MOVZ:
/* TODO: Implement emulation of Q8MOVZ instruction. */
MIPS_INVAL("OPC_MXU_Q8MOVZ");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8MOVN:
/* TODO: Implement emulation of Q8MOVN instruction. */
MIPS_INVAL("OPC_MXU_Q8MOVN");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16MOVZ:
/* TODO: Implement emulation of D16MOVZ instruction. */
MIPS_INVAL("OPC_MXU_D16MOVZ");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16MOVN:
/* TODO: Implement emulation of D16MOVN instruction. */
MIPS_INVAL("OPC_MXU_D16MOVN");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32MOVZ:
/* TODO: Implement emulation of S32MOVZ instruction. */
MIPS_INVAL("OPC_MXU_S32MOVZ");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32MOVN:
/* TODO: Implement emulation of S32MOVN instruction. */
MIPS_INVAL("OPC_MXU_S32MOVN");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27203,16 +27208,16 @@ static void decode_opc_mxu__pool21(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_Q8MAC:
/* TODO: Implement emulation of Q8MAC instruction. */
MIPS_INVAL("OPC_MXU_Q8MAC");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8MACSU:
/* TODO: Implement emulation of Q8MACSU instruction. */
MIPS_INVAL("OPC_MXU_Q8MACSU");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27271,12 +27276,12 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_S32MADD:
/* TODO: Implement emulation of S32MADD instruction. */
MIPS_INVAL("OPC_MXU_S32MADD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32MADDU:
/* TODO: Implement emulation of S32MADDU instruction. */
MIPS_INVAL("OPC_MXU_S32MADDU");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU__POOL00:
decode_opc_mxu__pool00(env, ctx);
@@ -27284,12 +27289,12 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_S32MSUB:
/* TODO: Implement emulation of S32MSUB instruction. */
MIPS_INVAL("OPC_MXU_S32MSUB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32MSUBU:
/* TODO: Implement emulation of S32MSUBU instruction. */
MIPS_INVAL("OPC_MXU_S32MSUBU");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU__POOL01:
decode_opc_mxu__pool01(env, ctx);
@@ -27309,27 +27314,27 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_D16MACF:
/* TODO: Implement emulation of D16MACF instruction. */
MIPS_INVAL("OPC_MXU_D16MACF");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16MADL:
/* TODO: Implement emulation of D16MADL instruction. */
MIPS_INVAL("OPC_MXU_D16MADL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S16MAD:
/* TODO: Implement emulation of S16MAD instruction. */
MIPS_INVAL("OPC_MXU_S16MAD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16ADD:
/* TODO: Implement emulation of Q16ADD instruction. */
MIPS_INVAL("OPC_MXU_Q16ADD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D16MACE:
/* TODO: Implement emulation of D16MACE instruction. */
MIPS_INVAL("OPC_MXU_D16MACE");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU__POOL04:
decode_opc_mxu__pool04(env, ctx);
@@ -27358,7 +27363,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_D32ADD:
/* TODO: Implement emulation of D32ADD instruction. */
MIPS_INVAL("OPC_MXU_D32ADD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU__POOL12:
decode_opc_mxu__pool12(env, ctx);
@@ -27372,7 +27377,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_Q8ACCE:
/* TODO: Implement emulation of Q8ACCE instruction. */
MIPS_INVAL("OPC_MXU_Q8ACCE");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S8LDD:
gen_mxu_s8ldd(ctx);
@@ -27380,17 +27385,17 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_S8STD:
/* TODO: Implement emulation of S8STD instruction. */
MIPS_INVAL("OPC_MXU_S8STD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S8LDI:
/* TODO: Implement emulation of S8LDI instruction. */
MIPS_INVAL("OPC_MXU_S8LDI");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S8SDI:
/* TODO: Implement emulation of S8SDI instruction. */
MIPS_INVAL("OPC_MXU_S8SDI");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU__POOL15:
decode_opc_mxu__pool15(env, ctx);
@@ -27404,52 +27409,52 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_S16LDD:
/* TODO: Implement emulation of S16LDD instruction. */
MIPS_INVAL("OPC_MXU_S16LDD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S16STD:
/* TODO: Implement emulation of S16STD instruction. */
MIPS_INVAL("OPC_MXU_S16STD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S16LDI:
/* TODO: Implement emulation of S16LDI instruction. */
MIPS_INVAL("OPC_MXU_S16LDI");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S16SDI:
/* TODO: Implement emulation of S16SDI instruction. */
MIPS_INVAL("OPC_MXU_S16SDI");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32SLL:
/* TODO: Implement emulation of D32SLL instruction. */
MIPS_INVAL("OPC_MXU_D32SLL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32SLR:
/* TODO: Implement emulation of D32SLR instruction. */
MIPS_INVAL("OPC_MXU_D32SLR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32SARL:
/* TODO: Implement emulation of D32SARL instruction. */
MIPS_INVAL("OPC_MXU_D32SARL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_D32SAR:
/* TODO: Implement emulation of D32SAR instruction. */
MIPS_INVAL("OPC_MXU_D32SAR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16SLL:
/* TODO: Implement emulation of Q16SLL instruction. */
MIPS_INVAL("OPC_MXU_Q16SLL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q16SLR:
/* TODO: Implement emulation of Q16SLR instruction. */
MIPS_INVAL("OPC_MXU_Q16SLR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU__POOL18:
decode_opc_mxu__pool18(env, ctx);
@@ -27457,7 +27462,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_Q16SAR:
/* TODO: Implement emulation of Q16SAR instruction. */
MIPS_INVAL("OPC_MXU_Q16SAR");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU__POOL19:
decode_opc_mxu__pool19(env, ctx);
@@ -27471,26 +27476,26 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
case OPC_MXU_Q16SCOP:
/* TODO: Implement emulation of Q16SCOP instruction. */
MIPS_INVAL("OPC_MXU_Q16SCOP");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8MADL:
/* TODO: Implement emulation of Q8MADL instruction. */
MIPS_INVAL("OPC_MXU_Q8MADL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_S32SFL:
/* TODO: Implement emulation of S32SFL instruction. */
MIPS_INVAL("OPC_MXU_S32SFL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_MXU_Q8SAD:
/* TODO: Implement emulation of Q8SAD instruction. */
MIPS_INVAL("OPC_MXU_Q8SAD");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
default:
MIPS_INVAL("decode_opc_mxu");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
gen_set_label(l_exit);
@@ -27569,7 +27574,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
#endif
default: /* Invalid */
MIPS_INVAL("special2_legacy");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27591,7 +27596,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
case R6_OPC_PREF:
if (rt >= 24) {
/* hint codes 24-31 are reserved and signal RI */
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
/* Treat as NOP. */
break;
@@ -27630,7 +27635,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
#ifndef CONFIG_USER_ONLY
case OPC_GINV:
if (unlikely(ctx->gi <= 1)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
check_cp0_enabled(ctx);
switch ((ctx->opcode >> 6) & 3) {
@@ -27641,7 +27646,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
gen_helper_0e1i(ginvt, cpu_gpr[rs], extract32(ctx->opcode, 8, 2));
break;
default:
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -27682,7 +27687,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
#endif
default: /* Invalid */
MIPS_INVAL("special3_r6");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -27733,13 +27738,13 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MASK ADDUH.QB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
} else if (ctx->insn_flags & INSN_LOONGSON2E) {
gen_loongson_integer(ctx, op1, rd, rs, rt);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
case OPC_LX_DSP:
@@ -27755,7 +27760,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK LX");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -27786,7 +27791,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MASK ABSQ_S.PH");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -27823,7 +27828,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK ADDU.QB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -27863,7 +27868,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK CMPU.EQ.QB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -27899,7 +27904,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK DPAW.PH");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -27929,7 +27934,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
default: /* Invalid */
MIPS_INVAL("MASK INSV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -27964,7 +27969,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK EXTR.W");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -28010,7 +28015,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK ABSQ_S.QH");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -28049,7 +28054,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK ADDU.OB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -28094,7 +28099,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK CMPU_EQ.OB");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -28131,7 +28136,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK EXTR.W");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -28170,7 +28175,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("MASK DPAQ.W.QH");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -28200,7 +28205,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
default: /* Invalid */
MIPS_INVAL("MASK DINSV");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -28210,7 +28215,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
#endif
default: /* Invalid */
MIPS_INVAL("special3_legacy");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -28248,11 +28253,11 @@ static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_0_PPACB: /* TODO: MMI_OPC_0_PPACB */
case MMI_OPC_0_PEXT5: /* TODO: MMI_OPC_0_PEXT5 */
case MMI_OPC_0_PPAC5: /* TODO: MMI_OPC_0_PPAC5 */
- generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI0 */
+ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI0 */
break;
default:
MIPS_INVAL("TX79 MMI class MMI0");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -28280,11 +28285,11 @@ static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_1_PSUBUB: /* TODO: MMI_OPC_1_PSUBUB */
case MMI_OPC_1_PEXTUB: /* TODO: MMI_OPC_1_PEXTUB */
case MMI_OPC_1_QFSRV: /* TODO: MMI_OPC_1_QFSRV */
- generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI1 */
+ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI1 */
break;
default:
MIPS_INVAL("TX79 MMI class MMI1");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -28315,14 +28320,14 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_2_PDIVBW: /* TODO: MMI_OPC_2_PDIVBW */
case MMI_OPC_2_PEXEW: /* TODO: MMI_OPC_2_PEXEW */
case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */
- generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 */
+ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */
break;
case MMI_OPC_2_PCPYLD:
gen_mmi_pcpyld(ctx);
break;
default:
MIPS_INVAL("TX79 MMI class MMI2");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -28343,7 +28348,7 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
- generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
+ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
case MMI_OPC_3_PCPYH:
gen_mmi_pcpyh(ctx);
@@ -28353,7 +28358,7 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -28407,23 +28412,23 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_PSLLW: /* TODO: MMI_OPC_PSLLW */
case MMI_OPC_PSRLW: /* TODO: MMI_OPC_PSRLW */
case MMI_OPC_PSRAW: /* TODO: MMI_OPC_PSRAW */
- generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI */
+ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI */
break;
default:
MIPS_INVAL("TX79 MMI class");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx)
{
- generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_LQ */
+ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_LQ */
}
static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
{
- generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_SQ */
+ gen_reserved_instruction(ctx); /* TODO: MMI_OPC_SQ */
}
/*
@@ -28631,7 +28636,7 @@ static inline int check_msa_access(DisasContext *ctx)
{
if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
!(ctx->hflags & MIPS_HFLAG_F64))) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return 0;
}
@@ -28640,7 +28645,7 @@ static inline int check_msa_access(DisasContext *ctx)
generate_exception_end(ctx, EXCP_MSADIS);
return 0;
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return 0;
}
}
@@ -28697,7 +28702,7 @@ static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1)
check_msa_access(ctx);
if (ctx->hflags & MIPS_HFLAG_BMASK) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
switch (op1) {
@@ -28772,7 +28777,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
{
uint8_t df = (ctx->opcode >> 24) & 0x3;
if (df == DF_DOUBLE) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
} else {
TCGv_i32 tdf = tcg_const_i32(df);
gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8);
@@ -28782,7 +28787,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -28854,7 +28859,7 @@ static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -28890,7 +28895,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
m = dfm & 0x7;
df = DF_BYTE;
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -28938,7 +28943,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -29783,7 +29788,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_HSUB_S_df:
case OPC_HSUB_U_df:
if (df == DF_BYTE) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
switch (MASK_MSA_3R(ctx->opcode)) {
@@ -29921,7 +29926,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
tcg_temp_free_i32(twd);
@@ -29953,7 +29958,7 @@ static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -29990,12 +29995,12 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
#if !defined(TARGET_MIPS64)
/* Double format valid only for MIPS64 */
if (df == DF_DOUBLE) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
if ((MASK_MSA_ELM(ctx->opcode) == OPC_COPY_U_df) &&
(df == DF_WORD)) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
#endif
@@ -30065,7 +30070,7 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
@@ -30095,7 +30100,7 @@ static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx)
gen_msa_elm_3e(env, ctx);
return;
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
return;
}
@@ -30250,7 +30255,7 @@ static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -30278,7 +30283,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
#if !defined(TARGET_MIPS64)
/* Double format valid only for MIPS64 */
if (df == DF_DOUBLE) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
#endif
@@ -30334,7 +30339,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -30449,7 +30454,7 @@ static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -30478,7 +30483,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -30576,7 +30581,7 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("MSA instruction");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
@@ -30660,7 +30665,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
/* OPC_NAL, OPC_BAL */
gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
} else {
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
@@ -30679,7 +30684,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SIGRIE:
check_insn(ctx, ISA_MIPS_R6);
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
case OPC_SYNCI:
check_insn(ctx, ISA_MIPS_R2);
@@ -30714,7 +30719,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
#endif
default: /* Invalid */
MIPS_INVAL("regimm");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -30823,7 +30828,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("mfmc0");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
tcg_temp_free(t0);
@@ -30840,7 +30845,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("cp0");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -30876,7 +30881,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */
if (ctx->insn_flags & ISA_MIPS_R6) {
if (rt == 0) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
/* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */
@@ -30889,7 +30894,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */
if (ctx->insn_flags & ISA_MIPS_R6) {
if (rt == 0) {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
/* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */
@@ -31138,7 +31143,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("cp1");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
break;
@@ -31224,7 +31229,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
default:
MIPS_INVAL("cp3");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
} else {
@@ -31289,7 +31294,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
} else {
MIPS_INVAL("major opcode");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
}
break;
#endif
@@ -31307,7 +31312,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
tcg_temp_free(t0);
}
#else
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
MIPS_INVAL("major opcode");
#endif
} else {
@@ -31333,7 +31338,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("major opcode");
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
break;
}
}
@@ -31438,7 +31443,7 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
insn_bytes = decode_mips16_opc(env, ctx);
} else {
- generate_exception_end(ctx, EXCP_RI);
+ gen_reserved_instruction(ctx);
g_assert(ctx->base.is_jmp == DISAS_NORETURN);
return;
}
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 32/69] target/mips: Declare generic FPU / Coprocessor functions in translate.h
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2021-01-14 16:20 ` [PULL v2 31/69] target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 35/69] target/mips/translate: Extract decode_opc_legacy() from decode_opc() Philippe Mathieu-Daudé
` (13 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
Some FPU / Coprocessor translation functions / registers can be
used by ISA / ASE / extensions out of the big translate.c file.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201214183739.500368-15-f4bug@amsat.org>
---
target/mips/translate.h | 12 ++++++++++++
target/mips/translate.c | 24 ++++++++++++------------
2 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 98cadffe4e5..a3f4a56750d 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -61,16 +61,28 @@ void check_insn(DisasContext *ctx, uint64_t flags);
#ifdef TARGET_MIPS64
void check_mips_64(DisasContext *ctx);
#endif
+void check_cp0_enabled(DisasContext *ctx);
+void check_cp1_enabled(DisasContext *ctx);
+void check_cp1_64bitmode(DisasContext *ctx);
+void check_cp1_registers(DisasContext *ctx, int regs);
+void check_cop1x(DisasContext *ctx);
void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
void gen_move_low32(TCGv ret, TCGv_i64 arg);
void gen_move_high32(TCGv ret, TCGv_i64 arg);
void gen_load_gpr(TCGv t, int reg);
void gen_store_gpr(TCGv t, int reg);
+void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
+void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
+void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
+void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
+int get_fp_bit(int cc);
void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
extern TCGv cpu_gpr[32], cpu_PC;
+extern TCGv_i32 fpu_fcr0, fpu_fcr31;
+extern TCGv_i64 fpu_f64[32];
extern TCGv bcond;
#define LOG_DISAS(...) \
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d7767215050..9b822344a2e 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2492,8 +2492,8 @@ static TCGv cpu_dspctrl, btarget;
TCGv bcond;
static TCGv cpu_lladdr, cpu_llval;
static TCGv_i32 hflags;
-static TCGv_i32 fpu_fcr0, fpu_fcr31;
-static TCGv_i64 fpu_f64[32];
+TCGv_i32 fpu_fcr0, fpu_fcr31;
+TCGv_i64 fpu_f64[32];
static TCGv_i64 msa_wr_d[64];
#if defined(TARGET_MIPS64)
@@ -2768,7 +2768,7 @@ void gen_reserved_instruction(DisasContext *ctx)
}
/* Floating point register moves. */
-static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
+void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_FRE) {
generate_exception(ctx, EXCP_RI);
@@ -2776,7 +2776,7 @@ static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
tcg_gen_extrl_i64_i32(t, fpu_f64[reg]);
}
-static void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
+void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg)
{
TCGv_i64 t64;
if (ctx->hflags & MIPS_HFLAG_FRE) {
@@ -2809,7 +2809,7 @@ static void gen_store_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg)
}
}
-static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
+void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64) {
tcg_gen_mov_i64(t, fpu_f64[reg]);
@@ -2818,7 +2818,7 @@ static void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
}
}
-static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
+void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
{
if (ctx->hflags & MIPS_HFLAG_F64) {
tcg_gen_mov_i64(fpu_f64[reg], t);
@@ -2832,7 +2832,7 @@ static void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
}
}
-static inline int get_fp_bit(int cc)
+int get_fp_bit(int cc)
{
if (cc) {
return 24 + cc;
@@ -2899,14 +2899,14 @@ void gen_move_high32(TCGv ret, TCGv_i64 arg)
#endif
}
-static inline void check_cp0_enabled(DisasContext *ctx)
+void check_cp0_enabled(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
generate_exception_end(ctx, EXCP_CpU);
}
}
-static inline void check_cp1_enabled(DisasContext *ctx)
+void check_cp1_enabled(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) {
generate_exception_err(ctx, EXCP_CpU, 1);
@@ -2918,7 +2918,7 @@ static inline void check_cp1_enabled(DisasContext *ctx)
* This is associated with the nabla symbol in the MIPS32 and MIPS64
* opcode tables.
*/
-static inline void check_cop1x(DisasContext *ctx)
+void check_cop1x(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) {
gen_reserved_instruction(ctx);
@@ -2929,7 +2929,7 @@ static inline void check_cop1x(DisasContext *ctx)
* Verify that the processor is running with 64-bit floating-point
* operations enabled.
*/
-static inline void check_cp1_64bitmode(DisasContext *ctx)
+void check_cp1_64bitmode(DisasContext *ctx)
{
if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) {
gen_reserved_instruction(ctx);
@@ -2947,7 +2947,7 @@ static inline void check_cp1_64bitmode(DisasContext *ctx)
* Multiple 64 bit wide registers can be checked by calling
* gen_op_cp1_registers(freg1 | freg2 | ... | fregN);
*/
-static inline void check_cp1_registers(DisasContext *ctx, int regs)
+void check_cp1_registers(DisasContext *ctx, int regs)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) {
gen_reserved_instruction(ctx);
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 35/69] target/mips/translate: Extract decode_opc_legacy() from decode_opc()
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2021-01-14 16:20 ` [PULL v2 32/69] target/mips: Declare generic FPU / Coprocessor functions in translate.h Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 36/69] target/mips/translate: Expose check_mips_64() to 32-bit mode Philippe Mathieu-Daudé
` (12 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
As we will slowly move to decodetree generated decoders,
extract the legacy decoding from decode_opc(), so new
decoders are added in decode_opc() while old code is
removed from decode_opc_legacy().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-2-f4bug@amsat.org>
---
target/mips/translate.c | 49 ++++++++++++++++++++++++-----------------
1 file changed, 29 insertions(+), 20 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4c400ec0b3c..d4d5d294f34 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -30517,30 +30517,13 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
}
-static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
+static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
{
int32_t offset;
int rs, rt, rd, sa;
uint32_t op, op1;
int16_t imm;
- /* make sure instructions are on a word boundary */
- if (ctx->base.pc_next & 0x3) {
- env->CP0_BadVAddr = ctx->base.pc_next;
- generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL);
- return;
- }
-
- /* Handle blikely not taken case */
- if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) {
- TCGLabel *l1 = gen_new_label();
-
- tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
- tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
- gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
- gen_set_label(l1);
- }
-
op = MASK_OP_MAJOR(ctx->opcode);
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
@@ -31268,9 +31251,35 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
break;
default: /* Invalid */
MIPS_INVAL("major opcode");
- gen_reserved_instruction(ctx);
- break;
+ return false;
}
+ return true;
+}
+
+static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
+{
+ /* make sure instructions are on a word boundary */
+ if (ctx->base.pc_next & 0x3) {
+ env->CP0_BadVAddr = ctx->base.pc_next;
+ generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL);
+ return;
+ }
+
+ /* Handle blikely not taken case */
+ if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) {
+ TCGLabel *l1 = gen_new_label();
+
+ tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
+ tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
+ gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
+ gen_set_label(l1);
+ }
+
+ if (decode_opc_legacy(env, ctx)) {
+ return;
+ }
+
+ gen_reserved_instruction(ctx);
}
static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 36/69] target/mips/translate: Expose check_mips_64() to 32-bit mode
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2021-01-14 16:20 ` [PULL v2 35/69] target/mips/translate: Extract decode_opc_legacy() from decode_opc() Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 52/69] target/mips: Introduce decode tree bindings for MSA ASE Philippe Mathieu-Daudé
` (11 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aurelien Jarno, Aleksandar Rikalo, qemu-devel,
Philippe Mathieu-Daudé
To allow compiling 64-bit specific translation code more
generically (and removing #ifdef'ry), allow compiling
check_mips_64() on 32-bit targets.
If ever called on 32-bit, we obviously emit a reserved
instruction exception.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Message-Id: <20201215225757.764263-3-f4bug@amsat.org>
---
target/mips/translate.h | 2 --
target/mips/translate.c | 8 +++-----
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 1b918a439b1..60e59675ef1 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -129,9 +129,7 @@ void generate_exception_end(DisasContext *ctx, int excp);
void gen_reserved_instruction(DisasContext *ctx);
void check_insn(DisasContext *ctx, uint64_t flags);
-#ifdef TARGET_MIPS64
void check_mips_64(DisasContext *ctx);
-#endif
void check_cp0_enabled(DisasContext *ctx);
void check_cp1_enabled(DisasContext *ctx);
void check_cp1_64bitmode(DisasContext *ctx);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d4d5d294f34..7e8afb363ac 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2971,18 +2971,16 @@ static inline void check_ps(DisasContext *ctx)
check_cp1_64bitmode(ctx);
}
-#ifdef TARGET_MIPS64
/*
- * This code generates a "reserved instruction" exception if 64-bit
- * instructions are not enabled.
+ * This code generates a "reserved instruction" exception if cpu is not
+ * 64-bit or 64-bit instructions are not enabled.
*/
void check_mips_64(DisasContext *ctx)
{
- if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
+ if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) {
gen_reserved_instruction(ctx);
}
}
-#endif
#ifndef CONFIG_USER_ONLY
static inline void check_mvh(DisasContext *ctx)
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 52/69] target/mips: Introduce decode tree bindings for MSA ASE
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2021-01-14 16:20 ` [PULL v2 36/69] target/mips/translate: Expose check_mips_64() to 32-bit mode Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 53/69] target/mips: Use decode_ase_msa() generated from decodetree Philippe Mathieu-Daudé
` (10 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
Introduce the 'msa32' decodetree config for the 32-bit MSA ASE.
We start by decoding:
- the branch instructions,
- all instructions based on the MSA opcode.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-20-f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
target/mips/translate.h | 3 +++
target/mips/msa32.decode | 24 ++++++++++++++++++++++++
target/mips/msa_translate.c | 36 ++++++++++++++++++++++++++++++++++++
target/mips/meson.build | 5 +++++
4 files changed, 68 insertions(+)
create mode 100644 target/mips/msa32.decode
diff --git a/target/mips/translate.h b/target/mips/translate.h
index ea9c18029d0..b61ae79d431 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -177,4 +177,7 @@ void msa_translate_init(void);
void gen_msa(DisasContext *ctx);
void gen_msa_branch(DisasContext *ctx, uint32_t op1);
+/* decodetree generated */
+bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
+
#endif
diff --git a/target/mips/msa32.decode b/target/mips/msa32.decode
new file mode 100644
index 00000000000..d69675132b8
--- /dev/null
+++ b/target/mips/msa32.decode
@@ -0,0 +1,24 @@
+# MIPS SIMD Architecture Module instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume IV-j
+# The MIPS32 SIMD Architecture Module, Revision 1.12
+# (Document Number: MD00866-2B-MSA32-AFP-01.12)
+#
+
+&msa_bz df wt s16
+
+@bz ...... ... .. wt:5 s16:16 &msa_bz df=3
+@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz
+
+BZ_V 010001 01011 ..... ................ @bz
+BNZ_V 010001 01111 ..... ................ @bz
+
+BZ_x 010001 110 .. ..... ................ @bz_df
+BNZ_x 010001 111 .. ..... ................ @bz_df
+
+MSA 011110 --------------------------
diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c
index 52bd428759a..5efb0a1fc8a 100644
--- a/target/mips/msa_translate.c
+++ b/target/mips/msa_translate.c
@@ -6,6 +6,7 @@
* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
* Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
* Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
+ * Copyright (c) 2020 Philippe Mathieu-Daudé
*
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
@@ -16,6 +17,9 @@
#include "fpu_helper.h"
#include "internal.h"
+/* Include the auto-generated decoder. */
+#include "decode-msa32.c.inc"
+
#define OPC_MSA (0x1E << 26)
#define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F))
@@ -370,6 +374,16 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
return true;
}
+static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a)
+{
+ return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ);
+}
+
+static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
+{
+ return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE);
+}
+
static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
{
check_msa_access(ctx);
@@ -388,6 +402,16 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not)
return true;
}
+static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a)
+{
+ return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false);
+}
+
+static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
+{
+ return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
+}
+
void gen_msa_branch(DisasContext *ctx, uint32_t op1)
{
uint8_t df = (ctx->opcode >> 21) & 0x3;
@@ -2261,3 +2285,15 @@ void gen_msa(DisasContext *ctx)
break;
}
}
+
+static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
+{
+ gen_msa(ctx);
+
+ return true;
+}
+
+bool decode_ase_msa(DisasContext *ctx, uint32_t insn)
+{
+ return decode_msa32(ctx, insn);
+}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 2aa4d81300b..a3c37241884 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,4 +1,9 @@
+gen = [
+ decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'),
+]
+
mips_ss = ss.source_set()
+mips_ss.add(gen)
mips_ss.add(files(
'cpu.c',
'gdbstub.c',
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 53/69] target/mips: Use decode_ase_msa() generated from decodetree
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2021-01-14 16:20 ` [PULL v2 52/69] target/mips: Introduce decode tree bindings for MSA ASE Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 54/69] target/mips: Extract LSA/DLSA translation generators Philippe Mathieu-Daudé
` (9 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
Now that we can decode the MSA ASE with decode_ase_msa(),
use it and remove the previous code, now unreachable.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-21-f4bug@amsat.org>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
target/mips/translate.h | 12 ------------
target/mips/msa_translate.c | 29 +----------------------------
target/mips/translate.c | 32 ++++++++++----------------------
3 files changed, 11 insertions(+), 62 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index b61ae79d431..9b38f82ecd9 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -82,8 +82,6 @@ enum {
OPC_BC1 = (0x08 << 21) | OPC_CP1, /* bc */
OPC_BC1ANY2 = (0x09 << 21) | OPC_CP1,
OPC_BC1ANY4 = (0x0A << 21) | OPC_CP1,
- OPC_BZ_V = (0x0B << 21) | OPC_CP1,
- OPC_BNZ_V = (0x0F << 21) | OPC_CP1,
OPC_S_FMT = (FMT_S << 21) | OPC_CP1,
OPC_D_FMT = (FMT_D << 21) | OPC_CP1,
OPC_E_FMT = (FMT_E << 21) | OPC_CP1,
@@ -93,14 +91,6 @@ enum {
OPC_PS_FMT = (FMT_PS << 21) | OPC_CP1,
OPC_BC1EQZ = (0x09 << 21) | OPC_CP1,
OPC_BC1NEZ = (0x0D << 21) | OPC_CP1,
- OPC_BZ_B = (0x18 << 21) | OPC_CP1,
- OPC_BZ_H = (0x19 << 21) | OPC_CP1,
- OPC_BZ_W = (0x1A << 21) | OPC_CP1,
- OPC_BZ_D = (0x1B << 21) | OPC_CP1,
- OPC_BNZ_B = (0x1C << 21) | OPC_CP1,
- OPC_BNZ_H = (0x1D << 21) | OPC_CP1,
- OPC_BNZ_W = (0x1E << 21) | OPC_CP1,
- OPC_BNZ_D = (0x1F << 21) | OPC_CP1,
};
#define MASK_CP1_FUNC(op) (MASK_CP1(op) | (op & 0x3F))
@@ -174,8 +164,6 @@ extern TCGv bcond;
/* MSA */
void msa_translate_init(void);
-void gen_msa(DisasContext *ctx);
-void gen_msa_branch(DisasContext *ctx, uint32_t op1);
/* decodetree generated */
bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c
index 5efb0a1fc8a..8a48f889aa2 100644
--- a/target/mips/msa_translate.c
+++ b/target/mips/msa_translate.c
@@ -412,33 +412,6 @@ static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
}
-void gen_msa_branch(DisasContext *ctx, uint32_t op1)
-{
- uint8_t df = (ctx->opcode >> 21) & 0x3;
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
- int64_t s16 = (int16_t)ctx->opcode;
-
- switch (op1) {
- case OPC_BZ_V:
- case OPC_BNZ_V:
- gen_msa_BxZ_V(ctx, wt, s16, (op1 == OPC_BZ_V) ?
- TCG_COND_EQ : TCG_COND_NE);
- break;
- case OPC_BZ_B:
- case OPC_BZ_H:
- case OPC_BZ_W:
- case OPC_BZ_D:
- gen_msa_BxZ(ctx, df, wt, s16, false);
- break;
- case OPC_BNZ_B:
- case OPC_BNZ_H:
- case OPC_BNZ_W:
- case OPC_BNZ_D:
- gen_msa_BxZ(ctx, df, wt, s16, true);
- break;
- }
-}
-
static void gen_msa_i8(DisasContext *ctx)
{
#define MASK_MSA_I8(op) (MASK_MSA_MINOR(op) | (op & (0x03 << 24)))
@@ -2188,7 +2161,7 @@ static void gen_msa_vec(DisasContext *ctx)
}
}
-void gen_msa(DisasContext *ctx)
+static void gen_msa(DisasContext *ctx)
{
uint32_t opcode = ctx->opcode;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index da5d5559160..6b59358b390 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6,6 +6,7 @@
* Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
* Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
* Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
+ * Copyright (c) 2020 Philippe Mathieu-Daudé
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -135,8 +136,6 @@ enum {
OPC_JIALC = (0x3E << 26),
/* MDMX ASE specific */
OPC_MDMX = (0x1E << 26),
- /* MSA ASE, same as MDMX */
- OPC_MSA = OPC_MDMX,
/* Cache and prefetch */
OPC_CACHE = (0x2F << 26),
OPC_PREF = (0x33 << 26),
@@ -28827,21 +28826,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
}
- case OPC_BZ_V:
- case OPC_BNZ_V:
- case OPC_BZ_B:
- case OPC_BZ_H:
- case OPC_BZ_W:
- case OPC_BZ_D:
- case OPC_BNZ_B:
- case OPC_BNZ_H:
- case OPC_BNZ_W:
- case OPC_BNZ_D:
- if (ase_msa_available(env)) {
- gen_msa_branch(ctx, op1);
- break;
- }
- /* fall through */
default:
MIPS_INVAL("cp1");
gen_reserved_instruction(ctx);
@@ -29023,16 +29007,13 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
}
break;
- case OPC_MSA: /* OPC_MDMX */
+ case OPC_MDMX: /* MMI_OPC_LQ */
if (ctx->insn_flags & INSN_R5900) {
#if defined(TARGET_MIPS64)
- gen_mmi_lq(env, ctx); /* MMI_OPC_LQ */
+ gen_mmi_lq(env, ctx);
#endif
} else {
/* MDMX: Not implemented. */
- if (ase_msa_available(env)) {
- gen_msa(ctx);
- }
}
break;
case OPC_PCREL:
@@ -29065,6 +29046,13 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
gen_set_label(l1);
}
+ /* Transition to the auto-generated decoder. */
+
+ /* ISA extensions */
+ if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
+ return;
+ }
+
if (decode_opc_legacy(env, ctx)) {
return;
}
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 54/69] target/mips: Extract LSA/DLSA translation generators
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2021-01-14 16:20 ` [PULL v2 53/69] target/mips: Use decode_ase_msa() generated from decodetree Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 55/69] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Philippe Mathieu-Daudé
` (8 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
Extract gen_lsa() from translate.c and explode it as
gen_LSA() and gen_DLSA().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-22-f4bug@amsat.org>
---
target/mips/translate.h | 5 +++
target/mips/translate.c | 36 ++----------------
target/mips/translate_addr_const.c | 61 ++++++++++++++++++++++++++++++
target/mips/meson.build | 1 +
4 files changed, 71 insertions(+), 32 deletions(-)
create mode 100644 target/mips/translate_addr_const.c
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 9b38f82ecd9..f93df0c5ab2 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -137,7 +137,12 @@ void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg);
void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg);
int get_fp_bit(int cc);
+/*
+ * Address Computation and Large Constant Instructions
+ */
void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1);
+bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
+bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa);
extern TCGv cpu_gpr[32], cpu_PC;
extern TCGv_i32 fpu_fcr0, fpu_fcr31;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6b59358b390..bed1a286f43 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6615,31 +6615,6 @@ static void gen_bshfl(DisasContext *ctx, uint32_t op2, int rt, int rd)
tcg_temp_free(t0);
}
-static void gen_lsa(DisasContext *ctx, int opc, int rd, int rs, int rt,
- int imm2)
-{
- TCGv t0;
- TCGv t1;
- if (rd == 0) {
- /* Treat as NOP. */
- return;
- }
- t0 = tcg_temp_new();
- t1 = tcg_temp_new();
- gen_load_gpr(t0, rs);
- gen_load_gpr(t1, rt);
- tcg_gen_shli_tl(t0, t0, imm2 + 1);
- tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
- if (opc == OPC_LSA) {
- tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
- }
-
- tcg_temp_free(t1);
- tcg_temp_free(t0);
-
- return;
-}
-
static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
int rt, int bits)
{
@@ -16495,8 +16470,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)
return;
case LSA:
check_insn(ctx, ISA_MIPS_R6);
- gen_lsa(ctx, OPC_LSA, rd, rs, rt,
- extract32(ctx->opcode, 9, 2));
+ gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2));
break;
case ALIGN:
check_insn(ctx, ISA_MIPS_R6);
@@ -21459,8 +21433,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
* amount, meaning that the supported shift values are in
* the range 0 to 3 (instead of 1 to 4 in MIPSR6).
*/
- gen_lsa(ctx, OPC_LSA, rd, rs, rt,
- extract32(ctx->opcode, 9, 2) - 1);
+ gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 9, 2) - 1);
break;
case NM_EXTW:
gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));
@@ -24346,7 +24319,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL(ctx->opcode);
switch (op1) {
case OPC_LSA:
- gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
+ gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2));
break;
case OPC_MULT:
case OPC_MULTU:
@@ -24399,8 +24372,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
break;
#if defined(TARGET_MIPS64)
case OPC_DLSA:
- check_mips_64(ctx);
- gen_lsa(ctx, op1, rd, rs, rt, extract32(ctx->opcode, 6, 2));
+ gen_dlsa(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2));
break;
case R6_OPC_DCLO:
case R6_OPC_DCLZ:
diff --git a/target/mips/translate_addr_const.c b/target/mips/translate_addr_const.c
new file mode 100644
index 00000000000..96f483418eb
--- /dev/null
+++ b/target/mips/translate_addr_const.c
@@ -0,0 +1,61 @@
+/*
+ * Address Computation and Large Constant Instructions
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2006 Marius Groeger (FPU operations)
+ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
+ * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support)
+ * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support)
+ * Copyright (c) 2020 Philippe Mathieu-Daudé
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "translate.h"
+
+bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
+{
+ TCGv t0;
+ TCGv t1;
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+ tcg_gen_shli_tl(t0, t0, sa + 1);
+ tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
+ tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]);
+
+ tcg_temp_free(t1);
+ tcg_temp_free(t0);
+
+ return true;
+}
+
+bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa)
+{
+ TCGv t0;
+ TCGv t1;
+
+ check_mips_64(ctx);
+
+ if (rd == 0) {
+ /* Treat as NOP. */
+ return true;
+ }
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+ gen_load_gpr(t1, rt);
+ tcg_gen_shli_tl(t0, t0, sa + 1);
+ tcg_gen_add_tl(cpu_gpr[rd], t0, t1);
+ tcg_temp_free(t1);
+ tcg_temp_free(t0);
+
+ return true;
+}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index a3c37241884..3810554343c 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -17,6 +17,7 @@
'op_helper.c',
'tlb_helper.c',
'translate.c',
+ 'translate_addr_const.c',
))
mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'))
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 55/69] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2021-01-14 16:20 ` [PULL v2 54/69] target/mips: Extract LSA/DLSA translation generators Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 56/69] target/mips: Introduce decodetree helpers for Release6 " Philippe Mathieu-Daudé
` (7 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
Add the LSA opcode to the MSA32 decodetree config, add DLSA
to a new config for the MSA64 ASE, and call decode_msa64()
in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-23-f4bug@amsat.org>
---
target/mips/msa32.decode | 5 +++++
target/mips/msa64.decode | 17 +++++++++++++++++
target/mips/msa_translate.c | 14 ++++++++++++++
target/mips/meson.build | 1 +
4 files changed, 37 insertions(+)
create mode 100644 target/mips/msa64.decode
diff --git a/target/mips/msa32.decode b/target/mips/msa32.decode
index d69675132b8..ca200e373b1 100644
--- a/target/mips/msa32.decode
+++ b/target/mips/msa32.decode
@@ -10,11 +10,16 @@
# (Document Number: MD00866-2B-MSA32-AFP-01.12)
#
+&rtype rs rt rd sa
+
&msa_bz df wt s16
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
@bz ...... ... .. wt:5 s16:16 &msa_bz df=3
@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz
+LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
+
BZ_V 010001 01011 ..... ................ @bz
BNZ_V 010001 01111 ..... ................ @bz
diff --git a/target/mips/msa64.decode b/target/mips/msa64.decode
new file mode 100644
index 00000000000..d2442474d0b
--- /dev/null
+++ b/target/mips/msa64.decode
@@ -0,0 +1,17 @@
+# MIPS SIMD Architecture Module instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume IV-j
+# The MIPS64 SIMD Architecture Module, Revision 1.12
+# (Document Number: MD00868-1D-MSA64-AFP-01.12)
+#
+
+&rtype rs rt rd sa !extern
+
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
+
+DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c
index 8a48f889aa2..ae6587edf69 100644
--- a/target/mips/msa_translate.c
+++ b/target/mips/msa_translate.c
@@ -19,6 +19,7 @@
/* Include the auto-generated decoder. */
#include "decode-msa32.c.inc"
+#include "decode-msa64.c.inc"
#define OPC_MSA (0x1E << 26)
@@ -2266,7 +2267,20 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
return true;
}
+static bool trans_LSA(DisasContext *ctx, arg_rtype *a)
+{
+ return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
+static bool trans_DLSA(DisasContext *ctx, arg_rtype *a)
+{
+ return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
bool decode_ase_msa(DisasContext *ctx, uint32_t insn)
{
+ if (TARGET_LONG_BITS == 64 && decode_msa64(ctx, insn)) {
+ return true;
+ }
return decode_msa32(ctx, insn);
}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 3810554343c..b63d8f150f1 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,5 +1,6 @@
gen = [
decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'),
+ decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'),
]
mips_ss = ss.source_set()
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 56/69] target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2021-01-14 16:20 ` [PULL v2 55/69] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 57/69] target/mips: Remove now unreachable LSA/DLSA opcodes code Philippe Mathieu-Daudé
` (6 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
LSA and LDSA opcodes are also available with MIPS release 6.
Introduce the decodetree config files and call the decode()
helpers in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-24-f4bug@amsat.org>
---
target/mips/translate.h | 1 +
target/mips/mips32r6.decode | 17 +++++++++++++++++
target/mips/mips64r6.decode | 17 +++++++++++++++++
target/mips/rel6_translate.c | 37 ++++++++++++++++++++++++++++++++++++
target/mips/translate.c | 5 +++++
target/mips/meson.build | 3 +++
6 files changed, 80 insertions(+)
create mode 100644 target/mips/mips32r6.decode
create mode 100644 target/mips/mips64r6.decode
create mode 100644 target/mips/rel6_translate.c
diff --git a/target/mips/translate.h b/target/mips/translate.h
index f93df0c5ab2..f47b5f2c8d0 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -171,6 +171,7 @@ extern TCGv bcond;
void msa_translate_init(void);
/* decodetree generated */
+bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
#endif
diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode
new file mode 100644
index 00000000000..d71a65f32cb
--- /dev/null
+++ b/target/mips/mips32r6.decode
@@ -0,0 +1,17 @@
+# MIPS32 Release 6 instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume II-A
+# The MIPS32 Instruction Set Reference Manual, Revision 6.06
+# (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06)
+#
+
+&rtype rs rt rd sa
+
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
+
+LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
diff --git a/target/mips/mips64r6.decode b/target/mips/mips64r6.decode
new file mode 100644
index 00000000000..fd58ac72414
--- /dev/null
+++ b/target/mips/mips64r6.decode
@@ -0,0 +1,17 @@
+# MIPS64 Release 6 instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume II-A
+# The MIPS64 Instruction Set Reference Manual, Revision 6.06
+# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06)
+#
+
+&rtype rs rt rd sa !extern
+
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
+
+DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
diff --git a/target/mips/rel6_translate.c b/target/mips/rel6_translate.c
new file mode 100644
index 00000000000..da70ff9662b
--- /dev/null
+++ b/target/mips/rel6_translate.c
@@ -0,0 +1,37 @@
+/*
+ * MIPS emulation for QEMU - # Release 6 translation routines
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2006 Marius Groeger (FPU operations)
+ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
+ * Copyright (c) 2020 Philippe Mathieu-Daudé
+ *
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "exec/helper-gen.h"
+#include "translate.h"
+
+/* Include the auto-generated decoder. */
+#include "decode-mips32r6.c.inc"
+#include "decode-mips64r6.c.inc"
+
+static bool trans_LSA(DisasContext *ctx, arg_rtype *a)
+{
+ return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
+static bool trans_DLSA(DisasContext *ctx, arg_rtype *a)
+{
+ return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
+bool decode_isa_rel6(DisasContext *ctx, uint32_t insn)
+{
+ if (TARGET_LONG_BITS == 64 && decode_mips64r6(ctx, insn)) {
+ return true;
+ }
+ return decode_mips32r6(ctx, insn);
+}
diff --git a/target/mips/translate.c b/target/mips/translate.c
index bed1a286f43..d297029a777 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29025,6 +29025,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
return;
}
+ /* ISA (from latest to oldest) */
+ if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->opcode)) {
+ return;
+ }
+
if (decode_opc_legacy(env, ctx)) {
return;
}
diff --git a/target/mips/meson.build b/target/mips/meson.build
index b63d8f150f1..9741545440c 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,4 +1,6 @@
gen = [
+ decodetree.process('mips32r6.decode', extra_args: '--static-decode=decode_mips32r6'),
+ decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'),
decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'),
decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'),
]
@@ -16,6 +18,7 @@
'msa_helper.c',
'msa_translate.c',
'op_helper.c',
+ 'rel6_translate.c',
'tlb_helper.c',
'translate.c',
'translate_addr_const.c',
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 57/69] target/mips: Remove now unreachable LSA/DLSA opcodes code
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2021-01-14 16:20 ` [PULL v2 56/69] target/mips: Introduce decodetree helpers for Release6 " Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 58/69] target/mips: Convert Rel6 Special2 opcode to decodetree Philippe Mathieu-Daudé
` (5 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
Since we switched to decodetree-generated processing,
we can remove this now unreachable code.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-6-f4bug@amsat.org>
---
target/mips/translate.c | 28 +++++-----------------------
1 file changed, 5 insertions(+), 23 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index d297029a777..e3bb1e83efe 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -280,9 +280,6 @@ enum {
R6_OPC_DCLZ = 0x12 | OPC_SPECIAL,
R6_OPC_DCLO = 0x13 | OPC_SPECIAL,
R6_OPC_SDBBP = 0x0e | OPC_SPECIAL,
-
- OPC_LSA = 0x05 | OPC_SPECIAL,
- OPC_DLSA = 0x15 | OPC_SPECIAL,
};
/* Multiplication variants of the vr54xx. */
@@ -24318,9 +24315,6 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL(ctx->opcode);
switch (op1) {
- case OPC_LSA:
- gen_lsa(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2));
- break;
case OPC_MULT:
case OPC_MULTU:
case OPC_DIV:
@@ -24371,9 +24365,6 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DLSA:
- gen_dlsa(ctx, rd, rt, rs, extract32(ctx->opcode, 6, 2));
- break;
case R6_OPC_DCLO:
case R6_OPC_DCLZ:
if (rt == 0 && sa == 1) {
@@ -24635,18 +24626,14 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
check_insn(ctx, ISA_MIPS2);
gen_trap(ctx, op1, rs, rt, -1);
break;
- case OPC_LSA: /* OPC_PMON */
- if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) {
- decode_opc_special_r6(env, ctx);
- } else {
- /* Pmon entry point, also R4010 selsl */
+ case OPC_PMON:
+ /* Pmon entry point, also R4010 selsl */
#ifdef MIPS_STRICT_STANDARD
- MIPS_INVAL("PMON / selsl");
- gen_reserved_instruction(ctx);
+ MIPS_INVAL("PMON / selsl");
+ gen_reserved_instruction(ctx);
#else
- gen_helper_0e0i(pmon, sa);
+ gen_helper_0e0i(pmon, sa);
#endif
- }
break;
case OPC_SYSCALL:
generate_exception_end(ctx, EXCP_SYSCALL);
@@ -24737,11 +24724,6 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
- case OPC_DLSA:
- if ((ctx->insn_flags & ISA_MIPS_R6) || ase_msa_available(env)) {
- decode_opc_special_r6(env, ctx);
- }
- break;
#endif
default:
if (ctx->insn_flags & ISA_MIPS_R6) {
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 58/69] target/mips: Convert Rel6 Special2 opcode to decodetree
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2021-01-14 16:20 ` [PULL v2 57/69] target/mips: Remove now unreachable LSA/DLSA opcodes code Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 63/69] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes " Philippe Mathieu-Daudé
` (4 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
Special2 opcode have been removed from the Release 6.
Add a single decodetree entry for all the opcode class,
triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() call.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-7-f4bug@amsat.org>
---
target/mips/mips32r6.decode | 2 ++
target/mips/rel6_translate.c | 7 +++++++
target/mips/translate.c | 2 --
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/mips/mips32r6.decode b/target/mips/mips32r6.decode
index d71a65f32cb..dd7faf75ab8 100644
--- a/target/mips/mips32r6.decode
+++ b/target/mips/mips32r6.decode
@@ -15,3 +15,5 @@
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
+
+REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2
diff --git a/target/mips/rel6_translate.c b/target/mips/rel6_translate.c
index da70ff9662b..139a7524eea 100644
--- a/target/mips/rel6_translate.c
+++ b/target/mips/rel6_translate.c
@@ -18,6 +18,13 @@
#include "decode-mips32r6.c.inc"
#include "decode-mips64r6.c.inc"
+bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a)
+{
+ gen_reserved_instruction(ctx);
+
+ return true;
+}
+
static bool trans_LSA(DisasContext *ctx, arg_rtype *a)
{
return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index e3bb1e83efe..2f23ce4a363 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -27136,8 +27136,6 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
int rs, rt, rd;
uint32_t op1;
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
-
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
rd = (ctx->opcode >> 11) & 0x1f;
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 63/69] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2021-01-14 16:20 ` [PULL v2 58/69] target/mips: Convert Rel6 Special2 opcode to decodetree Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 66/69] target/mips: Remove CPU_R5900 definition Philippe Mathieu-Daudé
` (3 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
LDL/LDR/SDL/SDR opcodes have been removed from the Release 6.
Add a single decodetree entry for the opcodes, triggering
Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201208203704.243704-12-f4bug@amsat.org>
---
target/mips/mips64r6.decode | 7 +++++++
target/mips/translate.c | 5 +----
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/mips/mips64r6.decode b/target/mips/mips64r6.decode
index fd58ac72414..8ca352a5c19 100644
--- a/target/mips/mips64r6.decode
+++ b/target/mips/mips64r6.decode
@@ -12,6 +12,13 @@
&rtype rs rt rd sa !extern
+&REMOVED !extern
+
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
+
+REMOVED 011010 ----- ----- ---------------- # LDL
+REMOVED 011011 ----- ----- ---------------- # LDR
+REMOVED 101100 ----- ----- ---------------- # SDL
+REMOVED 101101 ----- ----- ---------------- # SDR
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ffe283928bd..f0438ab9bef 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28870,11 +28870,10 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
if (ctx->insn_flags & INSN_R5900) {
check_insn_opc_user_only(ctx, INSN_R5900);
}
+ check_insn_opc_removed(ctx, ISA_MIPS_R6);
/* fall through */
case OPC_LDL:
case OPC_LDR:
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
- /* fall through */
case OPC_LWU:
case OPC_LD:
check_insn(ctx, ISA_MIPS3);
@@ -28883,8 +28882,6 @@ static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
break;
case OPC_SDL:
case OPC_SDR:
- check_insn_opc_removed(ctx, ISA_MIPS_R6);
- /* fall through */
case OPC_SD:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 66/69] target/mips: Remove CPU_R5900 definition
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2021-01-14 16:20 ` [PULL v2 63/69] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes " Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 67/69] target/mips: Remove CPU_NANOMIPS32 definition Philippe Mathieu-Daudé
` (2 subsequent siblings)
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
Commit 823f2897bdd ("target/mips: Disable R5900 support")
removed the single CPU using the CPU_R5900 definition.
As it is unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210112210152.2072996-2-f4bug@amsat.org>
---
target/mips/mips-defs.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 6b8e6800115..b7879be9e90 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -61,7 +61,6 @@
#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
-#define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 67/69] target/mips: Remove CPU_NANOMIPS32 definition
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2021-01-14 16:20 ` [PULL v2 66/69] target/mips: Remove CPU_R5900 definition Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 68/69] target/mips: Remove vendor specific CPU definitions Philippe Mathieu-Daudé
2021-01-15 15:26 ` [PULL v2 00/69] MIPS patches for 2021-01-14 Peter Maydell
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
nanoMIPS not a CPU, but an ISA. The nanoMIPS ISA is already
defined as ISA_NANOMIPS32.
Remove this incorrect definition and update the single CPU
implementing it, the I7200.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210112210152.2072996-3-f4bug@amsat.org>
---
target/mips/mips-defs.h | 3 ---
target/mips/cpu-defs.c.inc | 4 ++--
2 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index b7879be9e90..3704db85532 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -86,9 +86,6 @@
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6)
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
-/* Wave Computing: "nanoMIPS" */
-#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
-
#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
/*
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index ba22ff4bcd1..9f7bac87932 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -486,8 +486,8 @@ const mips_def_t mips_defs[] =
.CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008),
.SEGBITS = 32,
.PABITS = 32,
- .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 |
- ASE_MT,
+ .insn_flags = CPU_MIPS32R6 | ISA_NANOMIPS32 |
+ ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | ASE_MT,
.mmu_type = MMU_TYPE_R4000,
},
#if defined(TARGET_MIPS64)
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PULL v2 68/69] target/mips: Remove vendor specific CPU definitions
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2021-01-14 16:20 ` [PULL v2 67/69] target/mips: Remove CPU_NANOMIPS32 definition Philippe Mathieu-Daudé
@ 2021-01-14 16:20 ` Philippe Mathieu-Daudé
2021-01-15 15:26 ` [PULL v2 00/69] MIPS patches for 2021-01-14 Peter Maydell
17 siblings, 0 replies; 19+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-01-14 16:20 UTC (permalink / raw)
Cc: Aleksandar Rikalo, Richard Henderson, qemu-devel,
Philippe Mathieu-Daudé,
Aurelien Jarno
Vendor specific CPU definitions are not very useful. Use the
ISA definitions instead, which are more helpful when looking
at the various CPU definitions.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210112210152.2072996-4-f4bug@amsat.org>
---
target/mips/mips-defs.h | 5 -----
target/mips/cpu-defs.c.inc | 12 +++++++-----
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 3704db85532..0a12d982a72 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -60,9 +60,6 @@
#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
-#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
-#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
-#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI)
#define CPU_MIPS64 (ISA_MIPS3)
@@ -86,8 +83,6 @@
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS_R6)
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6)
-#define CPU_LOONGSON3A (CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT)
-
/*
* Strictly follow the architecture standard:
* - Disallow "special" instruction handling for PMON/SPIM.
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 9f7bac87932..e03b2a998cd 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -531,7 +531,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 32,
- .insn_flags = CPU_VR54XX,
+ .insn_flags = CPU_MIPS4 | INSN_VR54XX,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -781,7 +781,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 40,
- .insn_flags = CPU_LOONGSON2E,
+ .insn_flags = CPU_MIPS3 | INSN_LOONGSON2E,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -801,7 +801,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 40,
.PABITS = 40,
- .insn_flags = CPU_LOONGSON2F,
+ .insn_flags = CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -830,7 +830,8 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 42,
.PABITS = 48,
- .insn_flags = CPU_LOONGSON3A,
+ .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
+ ASE_LMMI | ASE_LEXT,
.mmu_type = MMU_TYPE_R4000,
},
{
@@ -887,7 +888,8 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 48,
.PABITS = 48,
- .insn_flags = CPU_LOONGSON3A,
+ .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A |
+ ASE_LMMI | ASE_LEXT,
.mmu_type = MMU_TYPE_R4000,
},
{
--
2.26.2
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PULL v2 00/69] MIPS patches for 2021-01-14
2021-01-14 16:19 [PULL v2 00/69] MIPS patches for 2021-01-14 Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2021-01-14 16:20 ` [PULL v2 68/69] target/mips: Remove vendor specific CPU definitions Philippe Mathieu-Daudé
@ 2021-01-15 15:26 ` Peter Maydell
17 siblings, 0 replies; 19+ messages in thread
From: Peter Maydell @ 2021-01-15 15:26 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Aleksandar Rikalo, QEMU Developers, Aurelien Jarno
On Thu, 14 Jan 2021 at 16:56, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> Resending the MIPS pull request from MIPS patches from last week
> (2021-01-07) now than the "decodetree: Open files with encoding='utf-8'"
> patch got merged (commit 4cacecaaa2b).
>
> ----------------------------------------------------------------
> MIPS patches queue
>
> - Simplify CPU/ISA definitions
> - Various maintenance code movements in translate.c
> - Convert part of the MSA ASE instructions to decodetree
> - Convert some instructions removed from Release 6 to decodetree
> - Remove deprecated 'fulong2e' machine alias
>
> ----------------------------------------------------------------
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2021-01-15 15:27 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
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2021-01-14 16:20 ` [PULL v2 52/69] target/mips: Introduce decode tree bindings for MSA ASE Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 53/69] target/mips: Use decode_ase_msa() generated from decodetree Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 54/69] target/mips: Extract LSA/DLSA translation generators Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 55/69] target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 56/69] target/mips: Introduce decodetree helpers for Release6 " Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 57/69] target/mips: Remove now unreachable LSA/DLSA opcodes code Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 58/69] target/mips: Convert Rel6 Special2 opcode to decodetree Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 63/69] target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes " Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 66/69] target/mips: Remove CPU_R5900 definition Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 67/69] target/mips: Remove CPU_NANOMIPS32 definition Philippe Mathieu-Daudé
2021-01-14 16:20 ` [PULL v2 68/69] target/mips: Remove vendor specific CPU definitions Philippe Mathieu-Daudé
2021-01-15 15:26 ` [PULL v2 00/69] MIPS patches for 2021-01-14 Peter Maydell
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