From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 19/33] target/arm: revector to run-time pick target EL
Date: Tue, 19 Jan 2021 15:10:50 +0000 [thread overview]
Message-ID: <20210119151104.16264-20-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210119151104.16264-1-peter.maydell@linaro.org>
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
On ARMv8-A, accesses by 32-bit secure EL1 to monitor registers trap to
the upper (64-bit) EL. With Secure EL2 support, we can no longer assume
that that is always EL3, so make room for the value to be computed at
run-time.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-16-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 528b93dffa2..614a6853ca5 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1094,6 +1094,22 @@ static void unallocated_encoding(DisasContext *s)
default_exception_el(s));
}
+static void gen_exception_el(DisasContext *s, int excp, uint32_t syn,
+ TCGv_i32 tcg_el)
+{
+ TCGv_i32 tcg_excp;
+ TCGv_i32 tcg_syn;
+
+ gen_set_condexec(s);
+ gen_set_pc_im(s, s->pc_curr);
+ tcg_excp = tcg_const_i32(excp);
+ tcg_syn = tcg_const_i32(syn);
+ gen_helper_exception_with_syndrome(cpu_env, tcg_excp, tcg_syn, tcg_el);
+ tcg_temp_free_i32(tcg_syn);
+ tcg_temp_free_i32(tcg_excp);
+ s->base.is_jmp = DISAS_NORETURN;
+}
+
/* Force a TB lookup after an instruction that changes the CPU state. */
static inline void gen_lookup_tb(DisasContext *s)
{
@@ -2818,8 +2834,11 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
/* If we're in Secure EL1 (which implies that EL3 is AArch64)
* then accesses to Mon registers trap to EL3
*/
- exc_target = 3;
- goto undef;
+ TCGv_i32 tcg_el = tcg_const_i32(3);
+
+ gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el);
+ tcg_temp_free_i32(tcg_el);
+ return false;
}
break;
case ARM_CPU_MODE_HYP:
--
2.20.1
next prev parent reply other threads:[~2021-01-19 15:33 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-19 15:10 [PULL 00/33] target-arm queue Peter Maydell
2021-01-19 15:10 ` [PULL 01/33] target/arm: Implement an IMPDEF pauth algorithm Peter Maydell
2021-01-19 15:10 ` [PULL 02/33] target/arm: Add cpu properties to control pauth Peter Maydell
2021-01-19 15:10 ` [PULL 03/33] target/arm: Use object_property_add_bool for "sve" property Peter Maydell
2021-01-19 15:10 ` [PULL 04/33] target/arm: remove redundant tests Peter Maydell
2021-01-19 15:10 ` [PULL 05/33] target/arm: add arm_is_el2_enabled() helper Peter Maydell
2021-01-19 15:10 ` [PULL 06/33] target/arm: use arm_is_el2_enabled() where applicable Peter Maydell
2021-01-19 15:10 ` [PULL 07/33] target/arm: use arm_hcr_el2_eff() " Peter Maydell
2021-01-19 15:10 ` [PULL 08/33] target/arm: factor MDCR_EL2 common handling Peter Maydell
2021-01-19 15:10 ` [PULL 09/33] target/arm: Define isar_feature function to test for presence of SEL2 Peter Maydell
2021-01-19 15:10 ` [PULL 10/33] target/arm: add 64-bit S-EL2 to EL exception table Peter Maydell
2021-01-19 15:10 ` [PULL 11/33] target/arm: add MMU stage 1 for Secure EL2 Peter Maydell
2021-01-19 15:10 ` [PULL 12/33] target/arm: add ARMv8.4-SEL2 system registers Peter Maydell
2021-01-19 15:10 ` [PULL 13/33] target/arm: handle VMID change in secure state Peter Maydell
2021-01-19 15:10 ` [PULL 14/33] target/arm: do S1_ptw_translate() before address space lookup Peter Maydell
2021-01-19 15:10 ` [PULL 15/33] target/arm: translate NS bit in page-walks Peter Maydell
2021-01-19 15:10 ` [PULL 16/33] target/arm: generalize 2-stage page-walk condition Peter Maydell
2021-01-19 15:10 ` [PULL 17/33] target/arm: secure stage 2 translation regime Peter Maydell
2021-01-19 15:10 ` [PULL 18/33] target/arm: set HPFAR_EL2.NS on secure stage 2 faults Peter Maydell
2021-01-19 15:10 ` Peter Maydell [this message]
2021-01-19 15:10 ` [PULL 20/33] target/arm: Implement SCR_EL2.EEL2 Peter Maydell
2021-01-19 15:10 ` [PULL 21/33] target/arm: enable Secure EL2 in max CPU Peter Maydell
2021-01-19 15:10 ` [PULL 22/33] target/arm: refactor vae1_tlbmask() Peter Maydell
2021-01-19 15:10 ` [PULL 23/33] target/arm: Introduce PREDDESC field definitions Peter Maydell
2021-01-19 15:10 ` [PULL 24/33] target/arm: Update PFIRST, PNEXT for pred_desc Peter Maydell
2021-01-19 15:10 ` [PULL 25/33] target/arm: Update ZIP, UZP, TRN " Peter Maydell
2021-01-19 15:10 ` [PULL 26/33] target/arm: Update REV, PUNPK " Peter Maydell
2021-01-19 15:10 ` [PULL 27/33] hw/misc/pvpanic: split-out generic and bus dependent code Peter Maydell
2021-01-19 15:10 ` [PULL 28/33] hw/misc/pvpanic: add PCI interface support Peter Maydell
2021-01-19 15:11 ` [PULL 29/33] pvpanic : update pvpanic spec document Peter Maydell
2021-01-19 15:11 ` [PULL 30/33] tests/qtest: add a test case for pvpanic-pci Peter Maydell
2021-01-19 15:11 ` [PULL 31/33] npcm7xx_adc-test: Fix memleak in adc_qom_set Peter Maydell
2021-01-19 15:11 ` [PULL 32/33] target/arm/m_helper: Silence GCC 10 maybe-uninitialized error Peter Maydell
2021-01-19 15:11 ` [PULL 33/33] docs: Build and install all the docs in a single manual Peter Maydell
2021-01-19 16:00 ` [PULL 00/33] target-arm queue no-reply
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