From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair23@gmail.com
Subject: [PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions
Date: Fri, 12 Feb 2021 23:02:53 +0800 [thread overview]
Message-ID: <20210212150256.885-36-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210212150256.885-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 12 ++
target/riscv/insn32-64.decode | 12 ++
target/riscv/insn_trans/trans_rvp.c.inc | 13 ++
target/riscv/packed_helper.c | 182 ++++++++++++++++++++++++
4 files changed, 219 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 05f7c1d811..85290a2b05 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1457,4 +1457,16 @@ DEF_HELPER_3(smtt32, tl, env, tl, tl)
DEF_HELPER_4(kmabb32, tl, env, tl, tl, tl)
DEF_HELPER_4(kmabt32, tl, env, tl, tl, tl)
DEF_HELPER_4(kmatt32, tl, env, tl, tl, tl)
+
+DEF_HELPER_3(kmda32, tl, env, tl, tl)
+DEF_HELPER_3(kmxda32, tl, env, tl, tl)
+DEF_HELPER_4(kmaxda32, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmads32, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmadrs32, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmaxds32, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmsda32, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmsxda32, tl, env, tl, tl, tl)
+DEF_HELPER_3(smds32, tl, env, tl, tl)
+DEF_HELPER_3(smdrs32, tl, env, tl, tl)
+DEF_HELPER_3(smxds32, tl, env, tl, tl)
#endif
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index c5b07a2667..ccdd965963 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -152,3 +152,15 @@ smtt32 0010100 ..... ..... 010 ..... 1111111 @r
kmabb32 0101101 ..... ..... 010 ..... 1111111 @r
kmabt32 0110101 ..... ..... 010 ..... 1111111 @r
kmatt32 0111101 ..... ..... 010 ..... 1111111 @r
+
+kmda32 0011100 ..... ..... 010 ..... 1111111 @r
+kmxda32 0011101 ..... ..... 010 ..... 1111111 @r
+kmaxda32 0100101 ..... ..... 010 ..... 1111111 @r
+kmads32 0101110 ..... ..... 010 ..... 1111111 @r
+kmadrs32 0110110 ..... ..... 010 ..... 1111111 @r
+kmaxds32 0111110 ..... ..... 010 ..... 1111111 @r
+kmsda32 0100110 ..... ..... 010 ..... 1111111 @r
+kmsxda32 0100111 ..... ..... 010 ..... 1111111 @r
+smds32 0101100 ..... ..... 010 ..... 1111111 @r
+smdrs32 0110100 ..... ..... 010 ..... 1111111 @r
+smxds32 0111100 ..... ..... 010 ..... 1111111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
index da6a4ba14a..d2000bcfb5 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -1199,4 +1199,17 @@ GEN_RVP_R_OOL(smtt32);
GEN_RVP_R_ACC_OOL(kmabb32);
GEN_RVP_R_ACC_OOL(kmabt32);
GEN_RVP_R_ACC_OOL(kmatt32);
+
+/* (RV64 Only) 32-bit Parallel Multiply & Add Instructions */
+GEN_RVP_R_OOL(kmda32);
+GEN_RVP_R_OOL(kmxda32);
+GEN_RVP_R_ACC_OOL(kmaxda32);
+GEN_RVP_R_ACC_OOL(kmads32);
+GEN_RVP_R_ACC_OOL(kmadrs32);
+GEN_RVP_R_ACC_OOL(kmaxds32);
+GEN_RVP_R_ACC_OOL(kmsda32);
+GEN_RVP_R_ACC_OOL(kmsxda32);
+GEN_RVP_R_OOL(smds32);
+GEN_RVP_R_OOL(smdrs32);
+GEN_RVP_R_OOL(smxds32);
#endif
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 99da28a4b3..bd24d5145a 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -3623,4 +3623,186 @@ static inline void do_kmatt32(CPURISCVState *env, void *vd, void *va,
}
RVPR_ACC(kmatt32, 1, sizeof(target_ulong));
+
+/* (RV64 Only) 32-bit Parallel Multiply & Add Instructions */
+static inline void do_kmda32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int64_t *d = vd;
+ int32_t *a = va, *b = vb;
+ if (a[H4(i)] == INT32_MIN && b[H4(i)] == INT32_MIN &&
+ a[H4(i + 1)] == INT32_MIN && b[H4(i + 1)] == INT32_MIN) {
+ *d = INT64_MAX;
+ env->vxsat = 0x1;
+ } else {
+ *d = (int64_t)a[H4(i)] * b[H4(i)] +
+ (int64_t)a[H4(i + 1)] * b[H4(i + 1)];
+ }
+}
+
+RVPR(kmda32, 1, sizeof(target_ulong));
+
+static inline void do_kmxda32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int64_t *d = vd;
+ int32_t *a = va, *b = vb;
+ if (a[H4(i)] == INT32_MIN && b[H4(i)] == INT32_MIN &&
+ a[H4(i + 1)] == INT32_MIN && b[H4(i + 1)] == INT32_MIN) {
+ *d = INT64_MAX;
+ env->vxsat = 0x1;
+ } else {
+ *d = (int64_t)a[H4(i)] * b[H4(i + 1)] +
+ (int64_t)a[H4(i + 1)] * b[H4(i)];
+ }
+}
+
+RVPR(kmxda32, 1, sizeof(target_ulong));
+
+static inline void do_kmaxda32(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int32_t *a = va, *b = vb;
+ int64_t p1, p2;
+ p1 = (int64_t)a[H4(i)] * b[H4(i + 1)];
+ p2 = (int64_t)a[H4(i + 1)] * b[H4(i)];
+
+ if (a[H4(i)] == INT32_MIN && a[H4(i + 1)] == INT32_MIN &&
+ b[H4(i)] == INT32_MIN && b[H4(i + 1)] == INT32_MIN) {
+ if (*d < 0) {
+ *d = (INT64_MAX + *c) + 1ll;
+ } else {
+ env->vxsat = 0x1;
+ *d = INT64_MAX;
+ }
+ } else {
+ *d = sadd64(env, 0, p1 + p2, *c);
+ }
+}
+
+RVPR_ACC(kmaxda32, 1, sizeof(target_ulong));
+
+static inline void do_kmads32(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int32_t *a = va, *b = vb;
+ int64_t t0, t1;
+ t1 = (int64_t)a[H4(i + 1)] * b[H4(i + 1)];
+ t0 = (int64_t)a[H4(i)] * b[H4(i)];
+
+ *d = sadd64(env, 0, t1 - t0, *c);
+}
+
+RVPR_ACC(kmads32, 1, sizeof(target_ulong));
+
+static inline void do_kmadrs32(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int32_t *a = va, *b = vb;
+ int64_t t0, t1;
+ t1 = (int64_t)a[H4(i + 1)] * b[H4(i + 1)];
+ t0 = (int64_t)a[H4(i)] * b[H4(i)];
+
+ *d = sadd64(env, 0, t0 - t1, *c);
+}
+
+RVPR_ACC(kmadrs32, 1, sizeof(target_ulong));
+
+static inline void do_kmaxds32(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int32_t *a = va, *b = vb;
+ int64_t t01, t10;
+ t01 = (int64_t)a[H4(i)] * b[H4(i + 1)];
+ t10 = (int64_t)a[H4(i + 1)] * b[H4(i)];
+
+ *d = sadd64(env, 0, t10 - t01, *c);
+}
+
+RVPR_ACC(kmaxds32, 1, sizeof(target_ulong));
+
+static inline void do_kmsda32(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int32_t *a = va, *b = vb;
+ int64_t t0, t1;
+ t0 = (int64_t)a[H4(i)] * b[H4(i)];
+ t1 = (int64_t)a[H4(i + 1)] * b[H4(i + 1)];
+
+ if (a[H4(i)] == INT32_MIN && a[H4(i + 1)] == INT32_MIN &&
+ b[H4(i)] == INT32_MIN && b[H4(i + 1)] == INT32_MIN) {
+ if (*d < 0) {
+ env->vxsat = 0x1;
+ *d = INT64_MIN;
+ } else {
+ *d = *c - 1ll - INT64_MAX;
+ }
+ } else {
+ *d = ssub64(env, 0, t0 + t1, *c);
+ }
+}
+
+RVPR_ACC(kmsda32, 1, sizeof(target_ulong));
+
+static inline void do_kmsxda32(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int32_t *a = va, *b = vb;
+ int64_t t01, t10;
+ t10 = (int64_t)a[H4(i + 1)] * b[H4(i)];
+ t01 = (int64_t)a[H4(i)] * b[H4(i + 1)];
+
+ if (a[H4(i)] == INT32_MIN && a[H4(i + 1)] == INT32_MIN &&
+ b[H4(i)] == INT32_MIN && b[H4(i + 1)] == INT32_MIN) {
+ if (*d < 0) {
+ env->vxsat = 0x1;
+ *d = INT64_MIN;
+ } else {
+ *d = *c - 1ll - INT64_MAX;
+ }
+ } else {
+ *d = ssub64(env, 0, t10 + t01, *c);
+ }
+}
+
+RVPR_ACC(kmsxda32, 1, sizeof(target_ulong));
+
+static inline void do_smds32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int64_t *d = vd;
+ int32_t *a = va, *b = vb;
+ *d = (int64_t)a[H4(i + 1)] * b[H4(i + 1)] -
+ (int64_t)a[H4(i)] * b[H4(i)];
+}
+
+RVPR(smds32, 1, sizeof(target_ulong));
+
+static inline void do_smdrs32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int64_t *d = vd;
+ int32_t *a = va, *b = vb;
+ *d = (int64_t)a[H4(i)] * b[H4(i)] -
+ (int64_t)a[H4(i + 1)] * b[H4(i + 1)];
+}
+
+RVPR(smdrs32, 1, sizeof(target_ulong));
+
+static inline void do_smxds32(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int64_t *d = vd;
+ int32_t *a = va, *b = vb;
+ *d = (int64_t)a[H4(i + 1)] * b[H4(i)] -
+ (int64_t)a[H4(i)] * b[H4(i + 1)];
+}
+
+RVPR(smxds32, 1, sizeof(target_ulong));
#endif
--
2.17.1
next prev parent reply other threads:[~2021-02-12 16:17 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-12 15:02 [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-02-12 15:02 ` [PATCH 01/38] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-03-09 14:08 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 02/38] target/riscv: Hoist vector functions LIU Zhiwei
2021-03-09 14:10 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 03/38] target/riscv: Fixup saturate subtract function LIU Zhiwei
2021-02-12 18:52 ` Richard Henderson
2021-03-09 14:11 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-02-12 18:03 ` Richard Henderson
2021-02-18 8:39 ` LIU Zhiwei
2021-02-18 16:20 ` Richard Henderson
2021-02-12 19:02 ` Richard Henderson
2021-02-18 8:47 ` LIU Zhiwei
2021-02-18 16:21 ` Richard Henderson
2021-02-12 15:02 ` [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-03-15 21:22 ` Alistair Francis
2021-05-24 1:00 ` Palmer Dabbelt
2021-05-26 5:43 ` LIU Zhiwei
2021-05-26 6:15 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-03-15 21:25 ` Alistair Francis
2021-03-16 2:40 ` LIU Zhiwei
2021-03-16 19:54 ` Alistair Francis
2021-03-17 2:30 ` LIU Zhiwei
2021-03-17 20:39 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 07/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:27 ` Alistair Francis
2021-05-24 4:46 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-03-15 21:28 ` Alistair Francis
2021-05-26 5:30 ` Palmer Dabbelt
2021-05-26 5:31 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 09/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:31 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 11/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:33 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-03-15 21:35 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 13/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-16 14:38 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-03-16 14:40 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 15/38] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-03-16 14:42 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 17/38] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-03-16 16:01 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-03-16 19:44 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 23/38] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 24/38] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 26/38] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 27/38] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 33/38] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-02-12 15:02 ` LIU Zhiwei [this message]
2021-02-12 15:02 ` [PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 38/38] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-03-05 6:14 ` [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-04-13 3:27 ` LIU Zhiwei
2021-04-15 4:46 ` Alistair Francis
2021-04-15 5:50 ` LIU Zhiwei
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