From: Alistair Francis <alistair23@gmail.com>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>
Cc: Richard Henderson <richard.henderson@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions
Date: Tue, 16 Mar 2021 15:44:17 -0400 [thread overview]
Message-ID: <CAKmqyKMDsJ8z6btDz9EsKnXN4sigGy_e1sg6=UUQizu+oNi=2A@mail.gmail.com> (raw)
In-Reply-To: <20210212150256.885-21-zhiwei_liu@c-sky.com>
On Fri, Feb 12, 2021 at 10:44 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/helper.h | 8 +++
> target/riscv/insn32-64.decode | 4 --
> target/riscv/insn32.decode | 10 ++++
> target/riscv/insn_trans/trans_rvp.c.inc | 9 +++
> target/riscv/packed_helper.c | 75 +++++++++++++++++++++++++
> 5 files changed, 102 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 2511134610..7c3a0654d6 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1315,3 +1315,11 @@ DEF_HELPER_4(kmsda, tl, env, tl, tl, tl)
> DEF_HELPER_4(kmsxda, tl, env, tl, tl, tl)
>
> DEF_HELPER_3(smal, i64, env, i64, tl)
> +
> +DEF_HELPER_3(sclip32, tl, env, tl, tl)
> +DEF_HELPER_3(uclip32, tl, env, tl, tl)
> +DEF_HELPER_2(clrs32, tl, env, tl)
> +DEF_HELPER_2(clz32, tl, env, tl)
> +DEF_HELPER_2(clo32, tl, env, tl)
> +DEF_HELPER_3(pbsad, tl, env, tl, tl)
> +DEF_HELPER_4(pbsada, tl, env, tl, tl, tl)
> diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
> index 8157dee8b7..1094172210 100644
> --- a/target/riscv/insn32-64.decode
> +++ b/target/riscv/insn32-64.decode
> @@ -19,10 +19,6 @@
> # This is concatenated with insn32.decode for risc64 targets.
> # Most of the fields and formats are there.
>
> -%sh5 20:5
> -
> -@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
> -
> # *** RV64I Base Instruction Set (in addition to RV32I) ***
> lwu ............ ..... 110 ..... 0000011 @i
> ld ............ ..... 011 ..... 0000011 @i
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index a022f660b7..12e95f9c5f 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -25,6 +25,7 @@
> %sh10 20:10
> %sh4 20:4
> %sh3 20:3
> +%sh5 20:5
> %csr 20:12
> %rm 12:3
> %nf 29:3 !function=ex_plus_1
> @@ -64,6 +65,7 @@
> @sh ...... ...... ..... ... ..... ....... &shift shamt=%sh10 %rs1 %rd
> @sh4 ...... ...... ..... ... ..... ....... &shift shamt=%sh4 %rs1 %rd
> @sh3 ...... ...... ..... ... ..... ....... &shift shamt=%sh3 %rs1 %rd
> +@sh5 ...... ...... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
> @csr ............ ..... ... ..... ....... %csr %rs1 %rd
>
> @atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
> @@ -783,3 +785,11 @@ kmsda 0100110 ..... ..... 001 ..... 1111111 @r
> kmsxda 0100111 ..... ..... 001 ..... 1111111 @r
>
> smal 0101111 ..... ..... 001 ..... 1111111 @r
> +
> +sclip32 1110010 ..... ..... 000 ..... 1111111 @sh5
> +uclip32 1111010 ..... ..... 000 ..... 1111111 @sh5
> +clrs32 1010111 11000 ..... 000 ..... 1111111 @r2
> +clz32 1010111 11001 ..... 000 ..... 1111111 @r2
> +clo32 1010111 11011 ..... 000 ..... 1111111 @r2
> +pbsad 1111110 ..... ..... 000 ..... 1111111 @r
> +pbsada 1111111 ..... ..... 000 ..... 1111111 @r
> diff --git a/target/riscv/insn_trans/trans_rvp.c.inc b/target/riscv/insn_trans/trans_rvp.c.inc
> index 73a26bbfbd..42656682c6 100644
> --- a/target/riscv/insn_trans/trans_rvp.c.inc
> +++ b/target/riscv/insn_trans/trans_rvp.c.inc
> @@ -656,3 +656,12 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
> }
>
> GEN_RVP_R_D64_S64_OOL(smal);
> +
> +/* Partial-SIMD Miscellaneous Instructions */
> +GEN_RVP_SHIFTI(sclip32, sclip32, NULL);
> +GEN_RVP_SHIFTI(uclip32, uclip32, NULL);
> +GEN_RVP_R2_OOL(clrs32);
> +GEN_RVP_R2_OOL(clz32);
> +GEN_RVP_R2_OOL(clo32);
> +GEN_RVP_R_OOL(pbsad);
> +GEN_RVP_R_ACC_OOL(pbsada);
> diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
> index 8ad7ea8354..96e73c045b 100644
> --- a/target/riscv/packed_helper.c
> +++ b/target/riscv/packed_helper.c
> @@ -1978,3 +1978,78 @@ uint64_t helper_smal(CPURISCVState *env, uint64_t a, target_ulong b)
> }
> return result;
> }
> +
> +/* Partial-SIMD Miscellaneous Instructions */
> +static inline void do_sclip32(CPURISCVState *env, void *vd, void *va,
> + void *vb, uint8_t i)
> +{
> + int32_t *d = vd, *a = va;
> + uint8_t shift = *(uint8_t *)vb & 0x1f;
> +
> + d[i] = sat64(env, a[i], shift);
> +}
> +
> +RVPR(sclip32, 1, 4);
> +
> +static inline void do_uclip32(CPURISCVState *env, void *vd, void *va,
> + void *vb, uint8_t i)
> +{
> + int32_t *d = vd, *a = va;
> + uint8_t shift = *(uint8_t *)vb & 0x1f;
> +
> + if (a[i] < 0) {
> + d[i] = 0;
> + env->vxsat = 0x1;
> + } else {
> + d[i] = satu64(env, a[i], shift);
> + }
> +}
> +
> +RVPR(uclip32, 1, 4);
> +
> +static inline void do_clrs32(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> + int32_t *d = vd, *a = va;
> + d[i] = clrsb32(a[i]);
> +}
> +
> +RVPR2(clrs32, 1, 4);
> +
> +static inline void do_clz32(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> + int32_t *d = vd, *a = va;
> + d[i] = clz32(a[i]);
> +}
> +
> +RVPR2(clz32, 1, 4);
> +
> +static inline void do_clo32(CPURISCVState *env, void *vd, void *va, uint8_t i)
> +{
> + int32_t *d = vd, *a = va;
> + d[i] = clo32(a[i]);
> +}
> +
> +RVPR2(clo32, 1, 4);
> +
> +static inline void do_pbsad(CPURISCVState *env, void *vd, void *va,
> + void *vb, uint8_t i)
> +{
> + target_ulong *d = vd;
> + uint8_t *a = va, *b = vb;
> + *d += abs(a[i] - b[i]);
> +}
> +
> +RVPR(pbsad, 1, 1);
> +
> +static inline void do_pbsada(CPURISCVState *env, void *vd, void *va,
> + void *vb, void *vc, uint8_t i)
> +{
> + target_ulong *d = vd, *c = vc;
> + uint8_t *a = va, *b = vb;
> + if (i == 0) {
> + *d += *c;
> + }
> + *d += abs(a[i] - b[i]);
> +}
> +
> +RVPR_ACC(pbsada, 1, 1);
> --
> 2.17.1
>
next prev parent reply other threads:[~2021-03-16 20:06 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-12 15:02 [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-02-12 15:02 ` [PATCH 01/38] target/riscv: implementation-defined constant parameters LIU Zhiwei
2021-03-09 14:08 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 02/38] target/riscv: Hoist vector functions LIU Zhiwei
2021-03-09 14:10 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 03/38] target/riscv: Fixup saturate subtract function LIU Zhiwei
2021-02-12 18:52 ` Richard Henderson
2021-03-09 14:11 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 04/38] target/riscv: 16-bit Addition & Subtraction Instructions LIU Zhiwei
2021-02-12 18:03 ` Richard Henderson
2021-02-18 8:39 ` LIU Zhiwei
2021-02-18 16:20 ` Richard Henderson
2021-02-12 19:02 ` Richard Henderson
2021-02-18 8:47 ` LIU Zhiwei
2021-02-18 16:21 ` Richard Henderson
2021-02-12 15:02 ` [PATCH 05/38] target/riscv: 8-bit Addition & Subtraction Instruction LIU Zhiwei
2021-03-15 21:22 ` Alistair Francis
2021-05-24 1:00 ` Palmer Dabbelt
2021-05-26 5:43 ` LIU Zhiwei
2021-05-26 6:15 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 06/38] target/riscv: SIMD 16-bit Shift Instructions LIU Zhiwei
2021-03-15 21:25 ` Alistair Francis
2021-03-16 2:40 ` LIU Zhiwei
2021-03-16 19:54 ` Alistair Francis
2021-03-17 2:30 ` LIU Zhiwei
2021-03-17 20:39 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 07/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:27 ` Alistair Francis
2021-05-24 4:46 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions LIU Zhiwei
2021-03-15 21:28 ` Alistair Francis
2021-05-26 5:30 ` Palmer Dabbelt
2021-05-26 5:31 ` Palmer Dabbelt
2021-02-12 15:02 ` [PATCH 09/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:31 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 11/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-15 21:33 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions LIU Zhiwei
2021-03-15 21:35 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 13/38] target/riscv: SIMD 8-bit " LIU Zhiwei
2021-03-16 14:38 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions LIU Zhiwei
2021-03-16 14:40 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 15/38] target/riscv: 16-bit Packing Instructions LIU Zhiwei
2021-03-16 14:42 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 17/38] target/riscv: Signed MSW 32x16 " LIU Zhiwei
2021-03-16 16:01 ` Alistair Francis
2021-02-12 15:02 ` [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions LIU Zhiwei
2021-03-16 19:44 ` Alistair Francis [this message]
2021-02-12 15:02 ` [PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 23/38] target/riscv: 32-bit Multiply " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 24/38] target/riscv: Signed 16-bit Multiply with " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 26/38] target/riscv: Non-SIMD Q31 " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 27/38] target/riscv: 32-bit Computation Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 28/38] target/riscv: Non-SIMD Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 33/38] target/riscv: RV64 Only 32-bit " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 35/38] target/riscv: RV64 Only 32-bit Parallel " LIU Zhiwei
2021-02-12 15:02 ` [PATCH 36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 37/38] target/riscv: RV64 Only 32-bit Packing Instructions LIU Zhiwei
2021-02-12 15:02 ` [PATCH 38/38] target/riscv: configure and turn on packed extension from command line LIU Zhiwei
2021-03-05 6:14 ` [PATCH 00/38] target/riscv: support packed extension v0.9.2 LIU Zhiwei
2021-04-13 3:27 ` LIU Zhiwei
2021-04-15 4:46 ` Alistair Francis
2021-04-15 5:50 ` LIU Zhiwei
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