From: Leif Lindholm <leif@nuviainc.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>,
qemu-arm <qemu-arm@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH] arm: bump amount of PMU counters to pass SBSA ACS
Date: Thu, 4 Mar 2021 13:53:04 +0000 [thread overview]
Message-ID: <20210304135304.GI1664@vanye> (raw)
In-Reply-To: <CAFEAcA-KFF_An50h8JKy68_Y3J4j=kQCOFyGoySKyh53E7KGYg@mail.gmail.com>
On Wed, Mar 03, 2021 at 18:06:46 +0000, Peter Maydell wrote:
> On Wed, 3 Mar 2021 at 17:48, Leif Lindholm <leif@nuviainc.com> wrote:
> > It would be good if we could get 6.0 closer to SBSA compliance.
>
> How far away are we at the moment ?
>
> > Would it be worth the effort to make this controllable per cpu model?
>
> I don't have a strong opinion on whether we should, but if we do then the
> right way to implement that would be to have the PMCR reset value
> as a reset_pmcr_el0 field in struct ARMCPU (like the existing reset_fpsid,
> reset_sctlr, etc) that gets set per-CPU to whatever the CPU's value for
> it is; and then instead of using a PMCR_NUM_COUNTERS value,
> extract the PMCR.N field when needed. The hardest part would be
> going through all the CPU TRMs to find out the correct reset value.
That makes sense.
I guess we could also phase the transition by using the default value
if zero?
Regards,
Leif
next prev parent reply other threads:[~2021-03-04 13:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-03 15:16 [PATCH] arm: bump amount of PMU counters to pass SBSA ACS Marcin Juszkiewicz
2021-03-03 17:48 ` Leif Lindholm
2021-03-03 18:06 ` Peter Maydell
2021-03-03 20:33 ` Marcin Juszkiewicz
2021-03-04 13:53 ` Leif Lindholm [this message]
2021-03-04 15:14 ` Peter Maydell
2021-03-04 15:25 ` Leif Lindholm
2021-03-11 17:02 ` Peter Maydell
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