From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>
Subject: [PATCH v8 00/78] support vector extension v1.0
Date: Fri, 15 Oct 2021 15:45:01 +0800 [thread overview]
Message-ID: <20211015074627.3957162-1-frank.chang@sifive.com> (raw)
From: Frank Chang <frank.chang@sifive.com>
This patchset implements the vector extension v1.0 for RISC-V on QEMU.
RVV v1.0 spec is now fronzen for public review:
https://github.com/riscv/riscv-v-spec/releases/tag/v1.0
The port is available here:
https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v8
RVV v1.0 can be enabled with -cpu option: v=true and specify vext_spec
option to v1.0 (i.e. vext_spec=v1.0)
Note: This patchset depends on other patchsets listed in Based-on
section below so it is not able to be built unless those patchsets
are applied.
Changelog:
v8
* Use {get,dest}_gpr APIs.
* remove vector AMO instructions.
* rename vpopc.m to vcpop.m.
* rename vle1.v and vse1.v to vlm.v and vsm.v.
* rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm.
v7
* remove hardcoded GDB vector registers list.
* add vsetivli instruction.
* add vle1.v and vse1.v instructions.
v6
* add vector floating-point reciprocal estimate instruction.
* add vector floating-point reciprocal square-root estimate instruction.
* update check rules for segment register groups, each segment register
group has to follow overlap rules.
* update viota.m instruction check rules.
v5
* refactor RVV v1.0 check functions.
(Thanks to Richard Henderson's bitwise tricks.)
* relax RV_VLEN_MAX to 1024-bits.
* implement vstart CSR's behaviors.
* trigger illegal instruction exception if frm is not valid for
vector floating-point instructions.
* rebase on riscv-to-apply.next.
v4
* remove explicit float flmul variable in DisasContext.
* replace floating-point calculations with shift operations to
improve performance.
* relax RV_VLEN_MAX to 512-bits.
v3
* apply nan-box helpers from Richard Henderson.
* remove fp16 api changes as they are sent independently in another
pathcset by Chih-Min Chao.
* remove all tail elements clear functions as tail elements can
retain unchanged for either VTA set to undisturbed or agnostic.
* add fp16 nan-box check generator function.
* add floating-point rounding mode enum.
* replace flmul arithmetic with shifts to avoid floating-point
conversions.
* add Zvqmac extension.
* replace gdbstub vector register xml files with dynamic generator.
* bumped to RVV v1.0.
* RVV v1.0 related changes:
* add vl<nf>re<eew>.v and vs<nf>r.v vector whole register
load/store instructions
* add vrgatherei16 instruction.
* rearranged bits in vtype to make vlmul bits into a contiguous
field.
v2
* drop v0.7.1 support.
* replace invisible return check macros with functions.
* move mark_vs_dirty() to translators.
* add SSTATUS_VS flag for s-mode.
* nan-box scalar fp register for floating-point operations.
* add gdbstub files for vector registers to allow system-mode
debugging with GDB.
Based-on: <20211015065500.3850513-1-frank.chang@sifive.com>
Based-on: <20211015070307.3860984-1-frank.chang@sifive.com>
Frank Chang (73):
target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh
target/riscv: drop vector 0.7.1 and add 1.0 support
target/riscv: Use FIELD_EX32() to extract wd field
target/riscv: rvv-1.0: introduce writable misa.v field
target/riscv: rvv-1.0: add translation-time vector context status
target/riscv: rvv-1.0: remove rvv related codes from fcsr registers
target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr
registers
target/riscv: rvv-1.0: remove MLEN calculations
target/riscv: rvv-1.0: add fractional LMUL
target/riscv: rvv-1.0: add VMA and VTA
target/riscv: rvv-1.0: update check functions
target/riscv: introduce more imm value modes in translator functions
target/riscv: rvv:1.0: add translation-time nan-box helper function
target/riscv: rvv-1.0: remove amo operations instructions
target/riscv: rvv-1.0: configure instructions
target/riscv: rvv-1.0: stride load and store instructions
target/riscv: rvv-1.0: index load and store instructions
target/riscv: rvv-1.0: fix address index overflow bug of indexed
load/store insns
target/riscv: rvv-1.0: fault-only-first unit stride load
target/riscv: rvv-1.0: load/store whole register instructions
target/riscv: rvv-1.0: update vext_max_elems() for load/store insns
target/riscv: rvv-1.0: take fractional LMUL into vector max elements
calculation
target/riscv: rvv-1.0: floating-point square-root instruction
target/riscv: rvv-1.0: floating-point classify instructions
target/riscv: rvv-1.0: count population in mask instruction
target/riscv: rvv-1.0: find-first-set mask bit instruction
target/riscv: rvv-1.0: set-X-first mask bit instructions
target/riscv: rvv-1.0: iota instruction
target/riscv: rvv-1.0: element index instruction
target/riscv: rvv-1.0: allow load element with sign-extended
target/riscv: rvv-1.0: register gather instructions
target/riscv: rvv-1.0: integer scalar move instructions
target/riscv: rvv-1.0: floating-point move instruction
target/riscv: rvv-1.0: floating-point scalar move instructions
target/riscv: rvv-1.0: whole register move instructions
target/riscv: rvv-1.0: integer extension instructions
target/riscv: rvv-1.0: single-width averaging add and subtract
instructions
target/riscv: rvv-1.0: single-width bit shift instructions
target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow
target/riscv: rvv-1.0: narrowing integer right shift instructions
target/riscv: rvv-1.0: widening integer multiply-add instructions
target/riscv: rvv-1.0: single-width saturating add and subtract
instructions
target/riscv: rvv-1.0: integer comparison instructions
target/riscv: rvv-1.0: floating-point compare instructions
target/riscv: rvv-1.0: mask-register logical instructions
target/riscv: rvv-1.0: slide instructions
target/riscv: rvv-1.0: floating-point slide instructions
target/riscv: rvv-1.0: narrowing fixed-point clip instructions
target/riscv: rvv-1.0: single-width floating-point reduction
target/riscv: rvv-1.0: widening floating-point reduction instructions
target/riscv: rvv-1.0: single-width scaling shift instructions
target/riscv: rvv-1.0: remove widening saturating scaled multiply-add
target/riscv: rvv-1.0: remove vmford.vv and vmford.vf
target/riscv: rvv-1.0: remove integer extract instruction
target/riscv: rvv-1.0: floating-point min/max instructions
target/riscv: introduce floating-point rounding mode enum
target/riscv: rvv-1.0: floating-point/integer type-convert
instructions
target/riscv: rvv-1.0: widening floating-point/integer type-convert
target/riscv: add "set round to odd" rounding mode helper function
target/riscv: rvv-1.0: narrowing floating-point/integer type-convert
target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
target/riscv: rvv-1.0: implement vstart CSR
target/riscv: rvv-1.0: trigger illegal instruction exception if frm is
not valid
target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs
target/riscv: rvv-1.0: floating-point reciprocal square-root estimate
instruction
target/riscv: rvv-1.0: floating-point reciprocal estimate instruction
target/riscv: set mstatus.SD bit when writing fp CSRs
target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
target/riscv: rvv-1.0: add vsetivli instruction
target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()
target/riscv: rvv-1.0: add vector unit-stride mask load/store insns
target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm
and vmorn.mm
target/riscv: rvv-1.0: update opivv_vadc_check() comment
Greentime Hu (1):
target/riscv: rvv-1.0: add vlenb register
Hsiangkai Wang (1):
target/riscv: gdb: support vector registers for rv64 & rv32
LIU Zhiwei (3):
target/riscv: rvv-1.0: add mstatus VS field
target/riscv: rvv-1.0: add sstatus VS field
target/riscv: rvv-1.0: add vcsr register
target/riscv/cpu.c | 12 +-
target/riscv/cpu.h | 85 +-
target/riscv/cpu_bits.h | 10 +
target/riscv/cpu_helper.c | 15 +-
target/riscv/csr.c | 92 +-
target/riscv/fpu_helper.c | 17 +-
target/riscv/gdbstub.c | 184 ++
target/riscv/helper.h | 435 ++-
target/riscv/insn32.decode | 294 +-
target/riscv/insn_trans/trans_rvv.c.inc | 2423 +++++++++------
target/riscv/internals.h | 24 +-
target/riscv/translate.c | 74 +-
target/riscv/vector_helper.c | 3601 ++++++++++++-----------
13 files changed, 4176 insertions(+), 3090 deletions(-)
--
2.25.1
next reply other threads:[~2021-10-15 7:48 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-15 7:45 frank.chang [this message]
2021-10-15 7:45 ` [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh frank.chang
2021-10-16 3:04 ` Richard Henderson
2021-10-17 22:55 ` Alistair Francis
2021-10-18 5:38 ` Richard Henderson
2021-10-18 6:01 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2021-10-15 7:45 ` [PATCH v8 03/78] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2021-10-15 7:45 ` [PATCH v8 04/78] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2021-10-15 7:45 ` [PATCH v8 05/78] target/riscv: rvv-1.0: add sstatus " frank.chang
2021-10-15 7:45 ` [PATCH v8 06/78] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2021-10-15 7:45 ` [PATCH v8 07/78] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2021-10-15 7:45 ` [PATCH v8 08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
2021-10-15 7:45 ` [PATCH v8 09/78] target/riscv: rvv-1.0: add vcsr register frank.chang
2021-10-15 7:45 ` [PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register frank.chang
2021-10-15 7:45 ` [PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2021-10-15 7:45 ` [PATCH v8 12/78] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2021-10-15 7:45 ` [PATCH v8 13/78] target/riscv: rvv-1.0: add fractional LMUL frank.chang
2021-10-15 7:45 ` [PATCH v8 14/78] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2021-10-15 7:45 ` [PATCH v8 15/78] target/riscv: rvv-1.0: update check functions frank.chang
2021-10-15 7:45 ` [PATCH v8 16/78] target/riscv: introduce more imm value modes in translator functions frank.chang
2021-10-15 7:45 ` [PATCH v8 17/78] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2021-10-15 7:45 ` [PATCH 18/76] target/riscv: rvv-1.0: configure instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 18/78] target/riscv: rvv-1.0: remove amo operations instructions frank.chang
2021-10-18 5:44 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 19/78] target/riscv: rvv-1.0: configure instructions frank.chang
2021-10-15 7:45 ` [PATCH 19/76] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2021-10-15 7:45 ` [PATCH 20/76] target/riscv: rvv-1.0: index " frank.chang
2021-10-15 7:45 ` [PATCH v8 20/78] target/riscv: rvv-1.0: stride " frank.chang
2021-10-15 7:45 ` [PATCH 21/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-10-15 7:45 ` [PATCH v8 21/78] target/riscv: rvv-1.0: index load and store instructions frank.chang
2021-10-15 7:45 ` [PATCH 22/76] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-10-15 7:45 ` [PATCH v8 22/78] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-10-15 7:45 ` [PATCH 23/76] target/riscv: rvv-1.0: amo operations frank.chang
2021-10-15 7:45 ` [PATCH v8 23/78] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-10-15 7:45 ` [PATCH v8 24/78] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 25/78] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2021-10-15 7:45 ` [PATCH v8 26/78] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2021-10-15 7:45 ` [PATCH v8 27/78] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2021-10-15 7:45 ` [PATCH v8 28/78] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 29/78] target/riscv: rvv-1.0: count population in mask instruction frank.chang
2021-10-18 5:46 ` Alistair Francis
2021-10-15 7:45 ` [PATCH 29/76] target/riscv: rvv-1.0: mask population count instruction frank.chang
2021-10-15 7:45 ` [PATCH v8 30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2021-10-18 5:47 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2021-10-18 5:53 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction frank.chang
2021-10-18 5:49 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction frank.chang
2021-10-18 5:54 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 34/78] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2021-10-21 4:28 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 35/78] target/riscv: rvv-1.0: register gather instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 36/78] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2021-10-21 4:24 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 37/78] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2021-10-15 7:45 ` [PATCH v8 38/78] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2021-10-21 4:26 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 39/78] target/riscv: rvv-1.0: whole register " frank.chang
2021-10-21 4:27 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 40/78] target/riscv: rvv-1.0: integer extension instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 41/78] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 42/78] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2021-10-25 6:08 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 44/78] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 45/78] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 46/78] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 47/78] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 48/78] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 49/78] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 50/78] target/riscv: rvv-1.0: slide instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 51/78] target/riscv: rvv-1.0: floating-point " frank.chang
2021-10-25 6:13 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 52/78] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 53/78] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2021-10-15 7:46 ` [PATCH v8 54/78] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 55/78] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 56/78] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2021-10-15 7:46 ` [PATCH v8 57/78] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
2021-10-15 7:46 ` [PATCH v8 58/78] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2021-10-15 7:46 ` [PATCH v8 59/78] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 60/78] target/riscv: introduce floating-point rounding mode enum frank.chang
2021-10-15 7:46 ` [PATCH v8 61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2021-10-25 6:16 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2021-10-26 6:29 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2021-10-26 6:30 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2021-10-26 6:32 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang
2021-10-25 6:43 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 66/78] target/riscv: rvv-1.0: implement vstart CSR frank.chang
2021-10-15 7:46 ` [PATCH v8 67/78] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang
2021-10-15 7:46 ` [PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang
2021-10-15 7:46 ` [PATCH v8 69/78] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang
2021-10-15 7:46 ` [PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang
2021-10-15 7:46 ` [PATCH v8 71/78] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang
2021-10-15 7:46 ` [PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang
2021-10-25 6:42 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang
2021-10-26 6:50 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 74/78] target/riscv: rvv-1.0: add vsetivli instruction frank.chang
2021-10-26 6:52 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 75/78] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang
2021-10-15 7:46 ` [PATCH v8 76/78] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang
2021-10-15 7:46 ` [PATCH v8 77/78] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm frank.chang
2021-10-26 6:55 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment frank.chang
2021-10-26 6:49 ` Alistair Francis
2021-10-15 9:02 ` [PATCH v8 00/78] support vector extension v1.0 Frank Chang
2021-10-18 6:00 ` Alistair Francis
2021-10-18 6:09 ` Frank Chang
2021-10-18 6:12 ` Alistair Francis
2021-10-18 6:17 ` Frank Chang
2021-10-18 9:01 ` LIU Zhiwei
2021-10-18 9:34 ` LIU Zhiwei
2021-10-20 5:28 ` Alistair Francis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211015074627.3957162-1-frank.chang@sifive.com \
--to=frank.chang@sifive.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).