From: Alistair Francis <alistair23@gmail.com>
To: Frank Chang <frank.chang@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v8 18/78] target/riscv: rvv-1.0: remove amo operations instructions
Date: Mon, 18 Oct 2021 15:44:13 +1000 [thread overview]
Message-ID: <CAKmqyKNkNp2SfFjzo0wzOCSyTj_1RbJFQb0KbA6dhGx_RtjW3w@mail.gmail.com> (raw)
In-Reply-To: <20211015074627.3957162-20-frank.chang@sifive.com>
On Fri, Oct 15, 2021 at 6:04 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Vector AMOs are removed from standard vector extensions. Will be added
> later as separate Zvamo extension, but will need a different encoding
> from earlier proposal.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/helper.h | 27 -----
> target/riscv/insn32.decode | 24 -----
> target/riscv/insn_trans/trans_rvv.c.inc | 137 ------------------------
> target/riscv/vector_helper.c | 125 ---------------------
> 4 files changed, 313 deletions(-)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index d25cf725c57..ecb6af6cd99 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -274,33 +274,6 @@ DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32)
> DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32)
> DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32)
> DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32)
> -DEF_HELPER_6(vamoswapw_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamoswapd_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamoaddw_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamoaddd_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamoxorw_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamoxord_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamoandw_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamoandd_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamoorw_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamoord_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamominw_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamomind_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamomaxw_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamomaxd_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamominuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamominud_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamomaxuw_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamomaxud_v_d, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamoswapw_v_w, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamoaddw_v_w, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamoxorw_v_w, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamoandw_v_w, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamoorw_v_w, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamominw_v_w, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamomaxw_v_w, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamominuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
> -DEF_HELPER_6(vamomaxuw_v_w, void, ptr, ptr, tl, ptr, env, i32)
>
> DEF_HELPER_6(vadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> DEF_HELPER_6(vadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 6c4cde216bc..3d57255fffb 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -49,7 +49,6 @@
> &atomic aq rl rs2 rs1 rd
> &rmrr vm rd rs1 rs2
> &rmr vm rd rs2
> -&rwdvm vm wd rd rs1 rs2
> &r2nfvm vm rd rs1 nf
> &rnfvm vm rd rs1 rs2 nf
>
> @@ -79,7 +78,6 @@
> @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
> @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
> @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
> -@r_wdvm ..... wd:1 vm:1 ..... ..... ... ..... ....... &rwdvm %rs2 %rs1 %rd
> @r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
> @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
>
> @@ -340,17 +338,6 @@ vsxh_v ... -11 . ..... ..... 101 ..... 0100111 @r_nfvm
> vsxw_v ... -11 . ..... ..... 110 ..... 0100111 @r_nfvm
> vsxe_v ... -11 . ..... ..... 111 ..... 0100111 @r_nfvm
>
> -#*** Vector AMO operations are encoded under the standard AMO major opcode ***
> -vamoswapw_v 00001 . . ..... ..... 110 ..... 0101111 @r_wdvm
> -vamoaddw_v 00000 . . ..... ..... 110 ..... 0101111 @r_wdvm
> -vamoxorw_v 00100 . . ..... ..... 110 ..... 0101111 @r_wdvm
> -vamoandw_v 01100 . . ..... ..... 110 ..... 0101111 @r_wdvm
> -vamoorw_v 01000 . . ..... ..... 110 ..... 0101111 @r_wdvm
> -vamominw_v 10000 . . ..... ..... 110 ..... 0101111 @r_wdvm
> -vamomaxw_v 10100 . . ..... ..... 110 ..... 0101111 @r_wdvm
> -vamominuw_v 11000 . . ..... ..... 110 ..... 0101111 @r_wdvm
> -vamomaxuw_v 11100 . . ..... ..... 110 ..... 0101111 @r_wdvm
> -
> # *** new major opcode OP-V ***
> vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm
> vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm
> @@ -649,17 +636,6 @@ vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
> vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
> vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
>
> -#*** Vector AMO operations (in addition to Zvamo) ***
> -vamoswapd_v 00001 . . ..... ..... 111 ..... 0101111 @r_wdvm
> -vamoaddd_v 00000 . . ..... ..... 111 ..... 0101111 @r_wdvm
> -vamoxord_v 00100 . . ..... ..... 111 ..... 0101111 @r_wdvm
> -vamoandd_v 01100 . . ..... ..... 111 ..... 0101111 @r_wdvm
> -vamoord_v 01000 . . ..... ..... 111 ..... 0101111 @r_wdvm
> -vamomind_v 10000 . . ..... ..... 111 ..... 0101111 @r_wdvm
> -vamomaxd_v 10100 . . ..... ..... 111 ..... 0101111 @r_wdvm
> -vamominud_v 11000 . . ..... ..... 111 ..... 0101111 @r_wdvm
> -vamomaxud_v 11100 . . ..... ..... 111 ..... 0101111 @r_wdvm
> -
> # *** RV32 Zba Standard Extension ***
> sh1add 0010000 .......... 010 ..... 0110011 @r
> sh2add 0010000 .......... 100 ..... 0110011 @r
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 50834bb8a39..ddea578d0ba 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -973,143 +973,6 @@ GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check)
> GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check)
> GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check)
>
> -/*
> - *** vector atomic operation
> - */
> -typedef void gen_helper_amo(TCGv_ptr, TCGv_ptr, TCGv, TCGv_ptr,
> - TCGv_env, TCGv_i32);
> -
> -static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
> - uint32_t data, gen_helper_amo *fn, DisasContext *s)
> -{
> - TCGv_ptr dest, mask, index;
> - TCGv base;
> - TCGv_i32 desc;
> -
> - TCGLabel *over = gen_new_label();
> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> -
> - dest = tcg_temp_new_ptr();
> - mask = tcg_temp_new_ptr();
> - index = tcg_temp_new_ptr();
> - base = get_gpr(s, rs1, EXT_NONE);
> - desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
> -
> - tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
> - tcg_gen_addi_ptr(index, cpu_env, vreg_ofs(s, vs2));
> - tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
> -
> - fn(dest, mask, base, index, cpu_env, desc);
> -
> - tcg_temp_free_ptr(dest);
> - tcg_temp_free_ptr(mask);
> - tcg_temp_free_ptr(index);
> - mark_vs_dirty(s);
> - gen_set_label(over);
> - return true;
> -}
> -
> -static bool amo_op(DisasContext *s, arg_rwdvm *a, uint8_t seq)
> -{
> - uint32_t data = 0;
> - gen_helper_amo *fn;
> - static gen_helper_amo *const fnsw[9] = {
> - /* no atomic operation */
> - gen_helper_vamoswapw_v_w,
> - gen_helper_vamoaddw_v_w,
> - gen_helper_vamoxorw_v_w,
> - gen_helper_vamoandw_v_w,
> - gen_helper_vamoorw_v_w,
> - gen_helper_vamominw_v_w,
> - gen_helper_vamomaxw_v_w,
> - gen_helper_vamominuw_v_w,
> - gen_helper_vamomaxuw_v_w
> - };
> - static gen_helper_amo *const fnsd[18] = {
> - gen_helper_vamoswapw_v_d,
> - gen_helper_vamoaddw_v_d,
> - gen_helper_vamoxorw_v_d,
> - gen_helper_vamoandw_v_d,
> - gen_helper_vamoorw_v_d,
> - gen_helper_vamominw_v_d,
> - gen_helper_vamomaxw_v_d,
> - gen_helper_vamominuw_v_d,
> - gen_helper_vamomaxuw_v_d,
> - gen_helper_vamoswapd_v_d,
> - gen_helper_vamoaddd_v_d,
> - gen_helper_vamoxord_v_d,
> - gen_helper_vamoandd_v_d,
> - gen_helper_vamoord_v_d,
> - gen_helper_vamomind_v_d,
> - gen_helper_vamomaxd_v_d,
> - gen_helper_vamominud_v_d,
> - gen_helper_vamomaxud_v_d
> - };
> -
> - if (tb_cflags(s->base.tb) & CF_PARALLEL) {
> - gen_helper_exit_atomic(cpu_env);
> - s->base.is_jmp = DISAS_NORETURN;
> - return true;
> - } else {
> - if (s->sew == 3) {
> - if (!is_32bit(s)) {
> - fn = fnsd[seq];
> - } else {
> - /* Check done in amo_check(). */
> - g_assert_not_reached();
> - }
> - } else {
> - assert(seq < ARRAY_SIZE(fnsw));
> - fn = fnsw[seq];
> - }
> - }
> -
> - data = FIELD_DP32(data, VDATA, VM, a->vm);
> - data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> - data = FIELD_DP32(data, VDATA, WD, a->wd);
> - return amo_trans(a->rd, a->rs1, a->rs2, data, fn, s);
> -}
> -/*
> - * There are two rules check here.
> - *
> - * 1. SEW must be at least as wide as the AMO memory element size.
> - *
> - * 2. If SEW is greater than XLEN, an illegal instruction exception is raised.
> - */
> -static bool amo_check(DisasContext *s, arg_rwdvm* a)
> -{
> - return (!s->vill && has_ext(s, RVA) &&
> - (!a->wd || vext_check_overlap_mask(s, a->rd, a->vm, false)) &&
> - vext_check_reg(s, a->rd, false) &&
> - vext_check_reg(s, a->rs2, false) &&
> - ((1 << s->sew) <= sizeof(target_ulong)) &&
> - ((1 << s->sew) >= 4));
> -}
> -
> -static bool amo_check64(DisasContext *s, arg_rwdvm* a)
> -{
> - return !is_32bit(s) && amo_check(s, a);
> -}
> -
> -GEN_VEXT_TRANS(vamoswapw_v, 0, rwdvm, amo_op, amo_check)
> -GEN_VEXT_TRANS(vamoaddw_v, 1, rwdvm, amo_op, amo_check)
> -GEN_VEXT_TRANS(vamoxorw_v, 2, rwdvm, amo_op, amo_check)
> -GEN_VEXT_TRANS(vamoandw_v, 3, rwdvm, amo_op, amo_check)
> -GEN_VEXT_TRANS(vamoorw_v, 4, rwdvm, amo_op, amo_check)
> -GEN_VEXT_TRANS(vamominw_v, 5, rwdvm, amo_op, amo_check)
> -GEN_VEXT_TRANS(vamomaxw_v, 6, rwdvm, amo_op, amo_check)
> -GEN_VEXT_TRANS(vamominuw_v, 7, rwdvm, amo_op, amo_check)
> -GEN_VEXT_TRANS(vamomaxuw_v, 8, rwdvm, amo_op, amo_check)
> -GEN_VEXT_TRANS(vamoswapd_v, 9, rwdvm, amo_op, amo_check64)
> -GEN_VEXT_TRANS(vamoaddd_v, 10, rwdvm, amo_op, amo_check64)
> -GEN_VEXT_TRANS(vamoxord_v, 11, rwdvm, amo_op, amo_check64)
> -GEN_VEXT_TRANS(vamoandd_v, 12, rwdvm, amo_op, amo_check64)
> -GEN_VEXT_TRANS(vamoord_v, 13, rwdvm, amo_op, amo_check64)
> -GEN_VEXT_TRANS(vamomind_v, 14, rwdvm, amo_op, amo_check64)
> -GEN_VEXT_TRANS(vamomaxd_v, 15, rwdvm, amo_op, amo_check64)
> -GEN_VEXT_TRANS(vamominud_v, 16, rwdvm, amo_op, amo_check64)
> -GEN_VEXT_TRANS(vamomaxud_v, 17, rwdvm, amo_op, amo_check64)
> -
> /*
> *** Vector Integer Arithmetic Instructions
> */
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index db1a40a3dbd..bf976d364f1 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -103,11 +103,6 @@ static inline int32_t vext_lmul(uint32_t desc)
> return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3);
> }
>
> -static uint32_t vext_wd(uint32_t desc)
> -{
> - return FIELD_EX32(simd_data(desc), VDATA, WD);
> -}
> -
> /*
> * Get vector group length in bytes. Its range is [64, 2048].
> *
> @@ -633,38 +628,12 @@ GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d)
> GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w)
> GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d)
>
> -/*
> - *** Vector AMO Operations (Zvamo)
> - */
> -typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr,
> - uint32_t wd, uint32_t idx, CPURISCVState *env,
> - uintptr_t retaddr);
> -
> -/* no atomic opreation for vector atomic insructions */
> #define DO_SWAP(N, M) (M)
> #define DO_AND(N, M) (N & M)
> #define DO_XOR(N, M) (N ^ M)
> #define DO_OR(N, M) (N | M)
> #define DO_ADD(N, M) (N + M)
>
> -#define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ESZ, MSZ, H, DO_OP, SUF) \
> -static void \
> -vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
> - uint32_t wd, uint32_t idx, \
> - CPURISCVState *env, uintptr_t retaddr)\
> -{ \
> - typedef int##ESZ##_t ETYPE; \
> - typedef int##MSZ##_t MTYPE; \
> - typedef uint##MSZ##_t UMTYPE __attribute__((unused)); \
> - ETYPE *pe3 = (ETYPE *)vs3 + H(idx); \
> - MTYPE a = cpu_ld##SUF##_data(env, addr), b = *pe3; \
> - \
> - cpu_st##SUF##_data(env, addr, DO_OP(a, b)); \
> - if (wd) { \
> - *pe3 = a; \
> - } \
> -}
> -
> /* Signed min/max */
> #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M))
> #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N))
> @@ -673,100 +642,6 @@ vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \
> #define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M)
> #define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
>
> -GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_w, 32, 32, H4, DO_SWAP, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_w, 32, 32, H4, DO_ADD, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_w, 32, 32, H4, DO_XOR, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_w, 32, 32, H4, DO_AND, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_w, 32, 32, H4, DO_OR, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_MIN, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamoaddd_v_d, 64, 64, H8, DO_ADD, q)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_d, 64, 32, H8, DO_XOR, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamoxord_v_d, 64, 64, H8, DO_XOR, q)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_d, 64, 32, H8, DO_AND, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamoandd_v_d, 64, 64, H8, DO_AND, q)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_d, 64, 32, H8, DO_OR, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamoord_v_d, 64, 64, H8, DO_OR, q)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_d, 64, 32, H8, DO_MIN, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamomind_v_d, 64, 64, H8, DO_MIN, q)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_d, 64, 32, H8, DO_MAX, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxd_v_d, 64, 64, H8, DO_MAX, q)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l)
> -GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q)
> -
> -static inline void
> -vext_amo_noatomic(void *vs3, void *v0, target_ulong base,
> - void *vs2, CPURISCVState *env, uint32_t desc,
> - vext_get_index_addr get_index_addr,
> - vext_amo_noatomic_fn *noatomic_op,
> - uint32_t esz, uint32_t msz, uintptr_t ra)
> -{
> - uint32_t i;
> - target_long addr;
> - uint32_t wd = vext_wd(desc);
> - uint32_t vm = vext_vm(desc);
> -
> - for (i = 0; i < env->vl; i++) {
> - if (!vm && !vext_elem_mask(v0, i)) {
> - continue;
> - }
> - probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD);
> - probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE);
> - }
> - for (i = 0; i < env->vl; i++) {
> - if (!vm && !vext_elem_mask(v0, i)) {
> - continue;
> - }
> - addr = get_index_addr(base, i, vs2);
> - noatomic_op(vs3, addr, wd, i, env, ra);
> - }
> -}
> -
> -#define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN) \
> -void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \
> - void *vs2, CPURISCVState *env, uint32_t desc) \
> -{ \
> - vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \
> - INDEX_FN, vext_##NAME##_noatomic_op, \
> - sizeof(ETYPE), sizeof(MTYPE), \
> - GETPC()); \
> -}
> -
> -GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d)
> -GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d)
> -GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d)
> -GEN_VEXT_AMO(vamoaddd_v_d, int64_t, int64_t, idx_d)
> -GEN_VEXT_AMO(vamoxorw_v_d, int32_t, int64_t, idx_d)
> -GEN_VEXT_AMO(vamoxord_v_d, int64_t, int64_t, idx_d)
> -GEN_VEXT_AMO(vamoandw_v_d, int32_t, int64_t, idx_d)
> -GEN_VEXT_AMO(vamoandd_v_d, int64_t, int64_t, idx_d)
> -GEN_VEXT_AMO(vamoorw_v_d, int32_t, int64_t, idx_d)
> -GEN_VEXT_AMO(vamoord_v_d, int64_t, int64_t, idx_d)
> -GEN_VEXT_AMO(vamominw_v_d, int32_t, int64_t, idx_d)
> -GEN_VEXT_AMO(vamomind_v_d, int64_t, int64_t, idx_d)
> -GEN_VEXT_AMO(vamomaxw_v_d, int32_t, int64_t, idx_d)
> -GEN_VEXT_AMO(vamomaxd_v_d, int64_t, int64_t, idx_d)
> -GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d)
> -GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d)
> -GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d)
> -GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d)
> -GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w)
> -GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w)
> -GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w)
> -GEN_VEXT_AMO(vamoandw_v_w, int32_t, int32_t, idx_w)
> -GEN_VEXT_AMO(vamoorw_v_w, int32_t, int32_t, idx_w)
> -GEN_VEXT_AMO(vamominw_v_w, int32_t, int32_t, idx_w)
> -GEN_VEXT_AMO(vamomaxw_v_w, int32_t, int32_t, idx_w)
> -GEN_VEXT_AMO(vamominuw_v_w, uint32_t, uint32_t, idx_w)
> -GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w)
> -
> /*
> *** Vector Integer Arithmetic Instructions
> */
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2021-10-18 5:47 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-15 7:45 [PATCH v8 00/78] support vector extension v1.0 frank.chang
2021-10-15 7:45 ` [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh frank.chang
2021-10-16 3:04 ` Richard Henderson
2021-10-17 22:55 ` Alistair Francis
2021-10-18 5:38 ` Richard Henderson
2021-10-18 6:01 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2021-10-15 7:45 ` [PATCH v8 03/78] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2021-10-15 7:45 ` [PATCH v8 04/78] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2021-10-15 7:45 ` [PATCH v8 05/78] target/riscv: rvv-1.0: add sstatus " frank.chang
2021-10-15 7:45 ` [PATCH v8 06/78] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2021-10-15 7:45 ` [PATCH v8 07/78] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2021-10-15 7:45 ` [PATCH v8 08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
2021-10-15 7:45 ` [PATCH v8 09/78] target/riscv: rvv-1.0: add vcsr register frank.chang
2021-10-15 7:45 ` [PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register frank.chang
2021-10-15 7:45 ` [PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2021-10-15 7:45 ` [PATCH v8 12/78] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2021-10-15 7:45 ` [PATCH v8 13/78] target/riscv: rvv-1.0: add fractional LMUL frank.chang
2021-10-15 7:45 ` [PATCH v8 14/78] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2021-10-15 7:45 ` [PATCH v8 15/78] target/riscv: rvv-1.0: update check functions frank.chang
2021-10-15 7:45 ` [PATCH v8 16/78] target/riscv: introduce more imm value modes in translator functions frank.chang
2021-10-15 7:45 ` [PATCH v8 17/78] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2021-10-15 7:45 ` [PATCH 18/76] target/riscv: rvv-1.0: configure instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 18/78] target/riscv: rvv-1.0: remove amo operations instructions frank.chang
2021-10-18 5:44 ` Alistair Francis [this message]
2021-10-15 7:45 ` [PATCH v8 19/78] target/riscv: rvv-1.0: configure instructions frank.chang
2021-10-15 7:45 ` [PATCH 19/76] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2021-10-15 7:45 ` [PATCH 20/76] target/riscv: rvv-1.0: index " frank.chang
2021-10-15 7:45 ` [PATCH v8 20/78] target/riscv: rvv-1.0: stride " frank.chang
2021-10-15 7:45 ` [PATCH 21/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-10-15 7:45 ` [PATCH v8 21/78] target/riscv: rvv-1.0: index load and store instructions frank.chang
2021-10-15 7:45 ` [PATCH 22/76] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-10-15 7:45 ` [PATCH v8 22/78] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-10-15 7:45 ` [PATCH 23/76] target/riscv: rvv-1.0: amo operations frank.chang
2021-10-15 7:45 ` [PATCH v8 23/78] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-10-15 7:45 ` [PATCH v8 24/78] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 25/78] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2021-10-15 7:45 ` [PATCH v8 26/78] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2021-10-15 7:45 ` [PATCH v8 27/78] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2021-10-15 7:45 ` [PATCH v8 28/78] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 29/78] target/riscv: rvv-1.0: count population in mask instruction frank.chang
2021-10-18 5:46 ` Alistair Francis
2021-10-15 7:45 ` [PATCH 29/76] target/riscv: rvv-1.0: mask population count instruction frank.chang
2021-10-15 7:45 ` [PATCH v8 30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2021-10-18 5:47 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2021-10-18 5:53 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction frank.chang
2021-10-18 5:49 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction frank.chang
2021-10-18 5:54 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 34/78] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2021-10-21 4:28 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 35/78] target/riscv: rvv-1.0: register gather instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 36/78] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2021-10-21 4:24 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 37/78] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2021-10-15 7:45 ` [PATCH v8 38/78] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2021-10-21 4:26 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 39/78] target/riscv: rvv-1.0: whole register " frank.chang
2021-10-21 4:27 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 40/78] target/riscv: rvv-1.0: integer extension instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 41/78] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 42/78] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2021-10-25 6:08 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 44/78] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 45/78] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 46/78] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 47/78] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 48/78] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 49/78] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 50/78] target/riscv: rvv-1.0: slide instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 51/78] target/riscv: rvv-1.0: floating-point " frank.chang
2021-10-25 6:13 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 52/78] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 53/78] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2021-10-15 7:46 ` [PATCH v8 54/78] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 55/78] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 56/78] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2021-10-15 7:46 ` [PATCH v8 57/78] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
2021-10-15 7:46 ` [PATCH v8 58/78] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2021-10-15 7:46 ` [PATCH v8 59/78] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 60/78] target/riscv: introduce floating-point rounding mode enum frank.chang
2021-10-15 7:46 ` [PATCH v8 61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2021-10-25 6:16 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2021-10-26 6:29 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2021-10-26 6:30 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2021-10-26 6:32 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang
2021-10-25 6:43 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 66/78] target/riscv: rvv-1.0: implement vstart CSR frank.chang
2021-10-15 7:46 ` [PATCH v8 67/78] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang
2021-10-15 7:46 ` [PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang
2021-10-15 7:46 ` [PATCH v8 69/78] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang
2021-10-15 7:46 ` [PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang
2021-10-15 7:46 ` [PATCH v8 71/78] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang
2021-10-15 7:46 ` [PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang
2021-10-25 6:42 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang
2021-10-26 6:50 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 74/78] target/riscv: rvv-1.0: add vsetivli instruction frank.chang
2021-10-26 6:52 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 75/78] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang
2021-10-15 7:46 ` [PATCH v8 76/78] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang
2021-10-15 7:46 ` [PATCH v8 77/78] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm frank.chang
2021-10-26 6:55 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment frank.chang
2021-10-26 6:49 ` Alistair Francis
2021-10-15 9:02 ` [PATCH v8 00/78] support vector extension v1.0 Frank Chang
2021-10-18 6:00 ` Alistair Francis
2021-10-18 6:09 ` Frank Chang
2021-10-18 6:12 ` Alistair Francis
2021-10-18 6:17 ` Frank Chang
2021-10-18 9:01 ` LIU Zhiwei
2021-10-18 9:34 ` LIU Zhiwei
2021-10-20 5:28 ` Alistair Francis
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