[PATCH v7 00/12] target/riscv: rework CPU extensions validation

[Daniel Henrique Barboza <dbarboza@ventanamicro.com>]

Hi,

In this v7 we have three extra patches: 

- patch 4 [1] and 5 [2], both from Weiwei Li, addresses an issue that
we're going to have with Zca and RVC if we push the priv spec
disabling code to the end of validation. More details can be seen on
[3]. Patch 5 commit message also has some context on it;

- patch 12 is something that was able to do with the recent changes from
Alistair's riscv-to-apply.next branch. We're using the bits from the
query-cpu-definitions work to filter out static CPUs from write_misa();

Patches missing acks: patch 12.

Patches based on top of current Alistair's riscv-to-apply.next.

Changes from v6:
- patches 4 and 5 from Weiwei Li were added
- patch 12 (new):
  - make write_misa a no-op when we're running a static CPU
- v6 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg06934.html


[1] https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg01010.html
[2] https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg01950.html
[3] https://lists.gnu.org/archive/html/qemu-devel/2023-04/msg00994.html

Daniel Henrique Barboza (10):
  target/riscv/cpu.c: add riscv_cpu_validate_v()
  target/riscv/cpu.c: remove set_vext_version()
  target/riscv/cpu.c: remove set_priv_version()
  target/riscv: add PRIV_VERSION_LATEST
  target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
  target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
  target/riscv/cpu.c: validate extensions before riscv_timer_init()
  target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
  target/riscv: rework write_misa()
  target/riscv: forbid write_misa() for static CPUs

Weiwei Li (2):
  target/riscv: Mask the implicitly enabled extensions in isa_string
    based on priv version
  target/riscv: Update check for Zca/Zcf/Zcd

 target/riscv/cpu.c                      | 338 ++++++++++++++----------
 target/riscv/cpu.h                      |   5 +
 target/riscv/csr.c                      |  48 ++--
 target/riscv/insn_trans/trans_rvd.c.inc |  12 +-
 target/riscv/insn_trans/trans_rvf.c.inc |  14 +-
 target/riscv/insn_trans/trans_rvi.c.inc |   5 +-
 target/riscv/translate.c                |   5 +-
 7 files changed, 254 insertions(+), 173 deletions(-)

-- 
2.39.2