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From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>,
	Junqiang Wang <wangjunqiang@iscas.ac.cn>,
	Alistair Francis <alistair.francis@wdc.com>,
	Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PULL 01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig
Date: Fri,  5 May 2023 11:01:13 +1000	[thread overview]
Message-ID: <20230505010241.21812-2-alistair.francis@wdc.com> (raw)
In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com>

From: Weiwei Li <liweiwei@iscas.ac.cn>

Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230309071329.45932-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c |  9 ++++-----
 target/riscv/csr.c        | 40 ++++++++++++---------------------------
 target/riscv/gdbstub.c    |  4 ++--
 3 files changed, 18 insertions(+), 35 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f88c503cf4..e677255f87 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -314,7 +314,6 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
                                     int extirq, unsigned int extirq_def_prio,
                                     uint64_t pending, uint8_t *iprio)
 {
-    RISCVCPU *cpu = env_archcpu(env);
     int irq, best_irq = RISCV_EXCP_NONE;
     unsigned int prio, best_prio = UINT_MAX;
 
@@ -323,7 +322,8 @@ static int riscv_cpu_pending_to_irq(CPURISCVState *env,
     }
 
     irq = ctz64(pending);
-    if (!((extirq == IRQ_M_EXT) ? cpu->cfg.ext_smaia : cpu->cfg.ext_ssaia)) {
+    if (!((extirq == IRQ_M_EXT) ? riscv_cpu_cfg(env)->ext_smaia :
+                                  riscv_cpu_cfg(env)->ext_ssaia)) {
         return irq;
     }
 
@@ -765,7 +765,6 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
     int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
     bool use_background = false;
     hwaddr ppn;
-    RISCVCPU *cpu = env_archcpu(env);
     int napot_bits = 0;
     target_ulong napot_mask;
 
@@ -946,7 +945,7 @@ restart:
 
         if (riscv_cpu_sxl(env) == MXL_RV32) {
             ppn = pte >> PTE_PPN_SHIFT;
-        } else if (pbmte || cpu->cfg.ext_svnapot) {
+        } else if (pbmte || riscv_cpu_cfg(env)->ext_svnapot) {
             ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
         } else {
             ppn = pte >> PTE_PPN_SHIFT;
@@ -1043,7 +1042,7 @@ restart:
                benefit. */
             target_ulong vpn = addr >> PGSHIFT;
 
-            if (cpu->cfg.ext_svnapot && (pte & PTE_N)) {
+            if (riscv_cpu_cfg(env)->ext_svnapot && (pte & PTE_N)) {
                 napot_bits = ctzl(ppn) + 1;
                 if ((i != (levels - 1)) || (napot_bits != 4)) {
                     return TRANSLATE_FAIL;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d522efc0b6..70468572fe 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -89,9 +89,7 @@ static RISCVException fs(CPURISCVState *env, int csrno)
 
 static RISCVException vs(CPURISCVState *env, int csrno)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
-    if (cpu->cfg.ext_zve32f) {
+    if (riscv_cpu_cfg(env)->ext_zve32f) {
 #if !defined(CONFIG_USER_ONLY)
         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
             return RISCV_EXCP_ILLEGAL_INST;
@@ -194,9 +192,7 @@ static RISCVException mctr32(CPURISCVState *env, int csrno)
 
 static RISCVException sscofpmf(CPURISCVState *env, int csrno)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
-    if (!cpu->cfg.ext_sscofpmf) {
+    if (!riscv_cpu_cfg(env)->ext_sscofpmf) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -311,9 +307,7 @@ static RISCVException umode32(CPURISCVState *env, int csrno)
 
 static RISCVException mstateen(CPURISCVState *env, int csrno)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
-    if (!cpu->cfg.ext_smstateen) {
+    if (!riscv_cpu_cfg(env)->ext_smstateen) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -322,9 +316,7 @@ static RISCVException mstateen(CPURISCVState *env, int csrno)
 
 static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
-    if (!cpu->cfg.ext_smstateen) {
+    if (!riscv_cpu_cfg(env)->ext_smstateen) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -391,10 +383,9 @@ static RISCVException sstateen(CPURISCVState *env, int csrno)
 
 static RISCVException sstc(CPURISCVState *env, int csrno)
 {
-    RISCVCPU *cpu = env_archcpu(env);
     bool hmode_check = false;
 
-    if (!cpu->cfg.ext_sstc || !env->rdtime_fn) {
+    if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
 
@@ -1171,27 +1162,21 @@ static RISCVException write_ignore(CPURISCVState *env, int csrno,
 static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
                                      target_ulong *val)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
-    *val = cpu->cfg.mvendorid;
+    *val = riscv_cpu_cfg(env)->mvendorid;
     return RISCV_EXCP_NONE;
 }
 
 static RISCVException read_marchid(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
-    *val = cpu->cfg.marchid;
+    *val = riscv_cpu_cfg(env)->marchid;
     return RISCV_EXCP_NONE;
 }
 
 static RISCVException read_mimpid(CPURISCVState *env, int csrno,
                                   target_ulong *val)
 {
-    RISCVCPU *cpu = env_archcpu(env);
-
-    *val = cpu->cfg.mimpid;
+    *val = riscv_cpu_cfg(env)->mimpid;
     return RISCV_EXCP_NONE;
 }
 
@@ -1233,9 +1218,8 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno,
 
 static bool validate_vm(CPURISCVState *env, target_ulong vm)
 {
-    RISCVCPU *cpu = RISCV_CPU(env_cpu(env));
-
-    return (vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map);
+    return (vm & 0xf) <=
+           satp_mode_max_from_map(riscv_cpu_cfg(env)->satp_mode.map);
 }
 
 static RISCVException write_mstatus(CPURISCVState *env, int csrno,
@@ -1898,7 +1882,7 @@ static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
 static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
                                     target_ulong val)
 {
-    RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
+    const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
     uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
 
     if (riscv_cpu_mxl(env) == MXL_RV64) {
@@ -1921,7 +1905,7 @@ static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
 static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
                                      target_ulong val)
 {
-    RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
+    const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
     uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
                     (cfg->ext_sstc ? MENVCFG_STCE : 0) |
                     (cfg->ext_svadu ? MENVCFG_HADE : 0);
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 840d1ec5c6..692bbb64f6 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -130,7 +130,7 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
 
 static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
 {
-    uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+    uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
     if (n < 32) {
         int i;
         int cnt = 0;
@@ -146,7 +146,7 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
 
 static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
 {
-    uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
+    uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;
     if (n < 32) {
         int i;
         for (i = 0; i < vlenb; i += 8) {
-- 
2.40.0



  reply	other threads:[~2023-05-05  1:03 UTC|newest]

Thread overview: 97+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-05  1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
2023-05-05  1:01 ` Alistair Francis [this message]
2023-05-05  1:01 ` [PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh Alistair Francis
2023-05-05  1:01 ` [PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env Alistair Francis
2023-05-05  1:01 ` [PULL 04/89] target/riscv: Simplify type conversion for CPURISCVState Alistair Francis
2023-05-05  1:01 ` [PULL 05/89] target/riscv: Simplify arguments for riscv_csrrw_check Alistair Francis
2023-05-05  1:01 ` [PULL 06/89] target/riscv: refactor Zicond support Alistair Francis
2023-05-05  1:01 ` [PULL 07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions Alistair Francis
2023-05-05  1:01 ` [PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry Alistair Francis
2023-05-05  1:01 ` [PULL 09/89] target/riscv: add cfg properties for Zc* extension Alistair Francis
2023-05-05  1:01 ` [PULL 10/89] target/riscv: add support for Zca extension Alistair Francis
2023-05-05  1:01 ` [PULL 11/89] target/riscv: add support for Zcf extension Alistair Francis
2023-05-05  1:01 ` [PULL 12/89] target/riscv: add support for Zcd extension Alistair Francis
2023-05-05  1:01 ` [PULL 13/89] target/riscv: add support for Zcb extension Alistair Francis
2023-05-05  1:01 ` [PULL 14/89] target/riscv: add support for Zcmp extension Alistair Francis
2023-05-05  1:01 ` [PULL 15/89] target/riscv: add support for Zcmt extension Alistair Francis
2023-05-05  1:01 ` [PULL 16/89] target/riscv: expose properties for Zc* extension Alistair Francis
2023-05-05  1:01 ` [PULL 17/89] disas/riscv.c: add disasm support for Zc* Alistair Francis
2023-05-05  1:01 ` [PULL 18/89] target/riscv: Add support for Zce Alistair Francis
2023-05-05  1:01 ` [PULL 19/89] target/riscv: Fix itrigger when icount is used Alistair Francis
2023-05-07 22:22   ` Alistair Francis
2023-05-10 17:17     ` Michael Tokarev
2023-05-05  1:01 ` [PULL 20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled Alistair Francis
2023-05-05  1:01 ` [PULL 21/89] target/riscv: Remove redundant check on RVH Alistair Francis
2023-05-05  1:01 ` [PULL 22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled Alistair Francis
2023-05-05  1:01 ` [PULL 23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled Alistair Francis
2023-05-05  1:01 ` [PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled Alistair Francis
2023-05-05  1:01 ` [PULL 25/89] target/riscv: Remove redundant parentheses Alistair Francis
2023-05-05  1:01 ` [PULL 26/89] target/riscv: Fix addr type for get_physical_address Alistair Francis
2023-05-05  1:01 ` [PULL 27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault Alistair Francis
2023-05-05  1:01 ` [PULL 28/89] target/riscv: Remove riscv_cpu_virt_enabled() Alistair Francis
2023-05-05  1:01 ` [PULL 29/89] target/riscv: Fix format for indentation Alistair Francis
2023-05-05  1:01 ` [PULL 30/89] target/riscv: Fix format for comments Alistair Francis
2023-05-05  1:01 ` [PULL 31/89] target/riscv: Fix lines with over 80 characters Alistair Francis
2023-05-05  1:01 ` [PULL 32/89] hw/riscv: Add signature dump function for spike to run ACT tests Alistair Francis
2023-05-05  1:01 ` [PULL 33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize() Alistair Francis
2023-05-05  1:01 ` [PULL 34/89] target/riscv: remove MISA properties from isa_edata_arr[] Alistair Francis
2023-05-05  1:01 ` [PULL 35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data Alistair Francis
2023-05-05  1:01 ` [PULL 36/89] target/riscv: introduce riscv_cpu_add_misa_properties() Alistair Francis
2023-05-05  1:01 ` [PULL 37/89] target/riscv: remove cpu->cfg.ext_a Alistair Francis
2023-05-05  1:01 ` [PULL 38/89] target/riscv: remove cpu->cfg.ext_c Alistair Francis
2023-05-05  1:01 ` [PULL 39/89] target/riscv: remove cpu->cfg.ext_d Alistair Francis
2023-05-05  1:01 ` [PULL 40/89] target/riscv: remove cpu->cfg.ext_f Alistair Francis
2023-05-05  1:01 ` [PULL 41/89] target/riscv: remove cpu->cfg.ext_i Alistair Francis
2023-05-05  1:01 ` [PULL 42/89] target/riscv: remove cpu->cfg.ext_e Alistair Francis
2023-05-05  1:01 ` [PULL 43/89] target/riscv: remove cpu->cfg.ext_m Alistair Francis
2023-05-05  1:01 ` [PULL 44/89] target/riscv: remove cpu->cfg.ext_s Alistair Francis
2023-05-05  1:01 ` [PULL 45/89] target/riscv: remove cpu->cfg.ext_u Alistair Francis
2023-05-05  1:01 ` [PULL 46/89] target/riscv: remove cpu->cfg.ext_h Alistair Francis
2023-05-05  1:01 ` [PULL 47/89] target/riscv: remove cpu->cfg.ext_j Alistair Francis
2023-05-05  1:02 ` [PULL 48/89] target/riscv: remove cpu->cfg.ext_v Alistair Francis
2023-05-05  1:02 ` [PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg() Alistair Francis
2023-05-05  1:02 ` [PULL 50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() Alistair Francis
2023-05-05  1:02 ` [PULL 51/89] target/riscv: add RVG and remove cpu->cfg.ext_g Alistair Francis
2023-05-05  1:02 ` [PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props() Alistair Francis
2023-05-05  1:02 ` [PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET Alistair Francis
2023-05-05  1:02 ` [PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H Alistair Francis
2023-05-05  1:02 ` [PULL 55/89] target/riscv: Legalize MPP value in write_mstatus Alistair Francis
2023-05-05  1:02 ` [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx Alistair Francis
2023-05-05  1:02 ` [PULL 57/89] target/riscv: fix H extension TVM trap Alistair Francis
2023-05-05  1:02 ` [PULL 58/89] target/riscv: Extract virt enabled state from tb flags Alistair Francis
2023-05-05  1:02 ` [PULL 59/89] target/riscv: Add a general status enum for extensions Alistair Francis
2023-05-05  1:02 ` [PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags Alistair Francis
2023-05-05  1:02 ` [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Alistair Francis
2023-05-05  1:02 ` [PULL 62/89] target/riscv: Add a tb flags field for vstart Alistair Francis
2023-05-05  1:02 ` [PULL 63/89] target/riscv: Separate priv from mmu_idx Alistair Francis
2023-05-05  1:02 ` [PULL 64/89] target/riscv: Reduce overhead of MSTATUS_SUM change Alistair Francis
2023-05-05  1:02 ` [PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX Alistair Francis
2023-05-05  1:02 ` [PULL 66/89] target/riscv: Handle HLV, HSV via helpers Alistair Francis
2023-05-05  1:02 ` [PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Alistair Francis
2023-05-05  1:02 ` [PULL 68/89] target/riscv: Introduce mmuidx_sum Alistair Francis
2023-05-05  1:02 ` [PULL 69/89] target/riscv: Introduce mmuidx_priv Alistair Francis
2023-05-05  1:02 ` [PULL 70/89] target/riscv: Introduce mmuidx_2stage Alistair Francis
2023-05-05  1:02 ` [PULL 71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv Alistair Francis
2023-05-05  1:02 ` [PULL 72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Alistair Francis
2023-05-05  1:02 ` [PULL 73/89] target/riscv: Check SUM in the correct register Alistair Francis
2023-05-05  1:02 ` [PULL 74/89] target/riscv: Hoist second stage mode change to callers Alistair Francis
2023-05-05  1:02 ` [PULL 75/89] target/riscv: Hoist pbmte and hade out of the level loop Alistair Francis
2023-05-05  1:02 ` [PULL 76/89] target/riscv: Move leaf pte processing out of " Alistair Francis
2023-05-05  1:02 ` [PULL 77/89] target/riscv: Suppress pte update with is_debug Alistair Francis
2023-05-05  1:02 ` [PULL 78/89] target/riscv: Don't modify SUM " Alistair Francis
2023-05-05  1:02 ` [PULL 79/89] target/riscv: Merge checks for reserved pte flags Alistair Francis
2023-05-05  1:02 ` [PULL 80/89] target/riscv: Reorg access check in get_physical_address Alistair Francis
2023-05-05  1:02 ` [PULL 81/89] target/riscv: Reorg sum " Alistair Francis
2023-05-05  1:02 ` [PULL 82/89] hw/intc/riscv_aplic: Zero init APLIC internal state Alistair Francis
2023-05-05  1:02 ` [PULL 83/89] target/riscv: add CPU QOM header Alistair Francis
2023-05-05  1:02 ` [PULL 84/89] target/riscv: add query-cpy-definitions support Alistair Francis
2023-05-05  1:02 ` [PULL 85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU Alistair Francis
2023-05-05  1:02 ` [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior Alistair Francis
2023-05-07 22:21   ` Alistair Francis
2023-05-10 17:18     ` Michael Tokarev
2023-05-05  1:02 ` [PULL 87/89] target/riscv: Fix Guest Physical Address Translation Alistair Francis
2023-05-05  1:02 ` [PULL 88/89] riscv: Make sure an exception is raised if a pte is malformed Alistair Francis
2023-05-05  1:02 ` [PULL 89/89] target/riscv: add Ventana's Veyron V1 CPU Alistair Francis
2023-05-05  1:05 ` [PULL 00/89] riscv-to-apply queue Alistair Francis
2023-05-05  1:08   ` Alistair Francis
2023-05-05 15:00 ` Richard Henderson

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