From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, "Weiwei Li" <liweiwei@iscas.ac.cn>,
"Junqiang Wang" <wangjunqiang@iscas.ac.cn>,
"Alistair Francis" <alistair.francis@wdc.com>,
"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 05/89] target/riscv: Simplify arguments for riscv_csrrw_check
Date: Fri, 5 May 2023 11:01:17 +1000 [thread overview]
Message-ID: <20230505010241.21812-6-alistair.francis@wdc.com> (raw)
In-Reply-To: <20230505010241.21812-1-alistair.francis@wdc.com>
From: Weiwei Li <liweiwei@iscas.ac.cn>
Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
directly.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230309071329.45932-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a7d0157d33..8f4d5eb13f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3756,15 +3756,14 @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
int csrno,
- bool write_mask,
- RISCVCPU *cpu)
+ bool write_mask)
{
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
bool read_only = get_field(csrno, 0xC00) == 3;
int csr_min_priv = csr_ops[csrno].min_priv_ver;
/* ensure the CSR extension is enabled */
- if (!cpu->cfg.ext_icsr) {
+ if (!riscv_cpu_cfg(env)->ext_icsr) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -3860,9 +3859,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
- RISCVCPU *cpu = env_archcpu(env);
-
- RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
+ RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
if (ret != RISCV_EXCP_NONE) {
return ret;
}
@@ -3915,9 +3912,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
Int128 new_value, Int128 write_mask)
{
RISCVException ret;
- RISCVCPU *cpu = env_archcpu(env);
- ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
+ ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
if (ret != RISCV_EXCP_NONE) {
return ret;
}
--
2.40.0
next prev parent reply other threads:[~2023-05-05 1:05 UTC|newest]
Thread overview: 97+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-05 1:01 [PULL 00/89] riscv-to-apply queue Alistair Francis
2023-05-05 1:01 ` [PULL 01/89] target/riscv: Avoid env_archcpu() when reading RISCVCPUConfig Alistair Francis
2023-05-05 1:01 ` [PULL 02/89] target/riscv: Fix priv version dependency for vector and zfh Alistair Francis
2023-05-05 1:01 ` [PULL 03/89] target/riscv: Simplify getting RISCVCPU pointer from env Alistair Francis
2023-05-05 1:01 ` [PULL 04/89] target/riscv: Simplify type conversion for CPURISCVState Alistair Francis
2023-05-05 1:01 ` Alistair Francis [this message]
2023-05-05 1:01 ` [PULL 06/89] target/riscv: refactor Zicond support Alistair Francis
2023-05-05 1:01 ` [PULL 07/89] target/riscv: redirect XVentanaCondOps to use the Zicond functions Alistair Francis
2023-05-05 1:01 ` [PULL 08/89] target/riscv: fix invalid riscv, event-to-mhpmcounters entry Alistair Francis
2023-05-05 1:01 ` [PULL 09/89] target/riscv: add cfg properties for Zc* extension Alistair Francis
2023-05-05 1:01 ` [PULL 10/89] target/riscv: add support for Zca extension Alistair Francis
2023-05-05 1:01 ` [PULL 11/89] target/riscv: add support for Zcf extension Alistair Francis
2023-05-05 1:01 ` [PULL 12/89] target/riscv: add support for Zcd extension Alistair Francis
2023-05-05 1:01 ` [PULL 13/89] target/riscv: add support for Zcb extension Alistair Francis
2023-05-05 1:01 ` [PULL 14/89] target/riscv: add support for Zcmp extension Alistair Francis
2023-05-05 1:01 ` [PULL 15/89] target/riscv: add support for Zcmt extension Alistair Francis
2023-05-05 1:01 ` [PULL 16/89] target/riscv: expose properties for Zc* extension Alistair Francis
2023-05-05 1:01 ` [PULL 17/89] disas/riscv.c: add disasm support for Zc* Alistair Francis
2023-05-05 1:01 ` [PULL 18/89] target/riscv: Add support for Zce Alistair Francis
2023-05-05 1:01 ` [PULL 19/89] target/riscv: Fix itrigger when icount is used Alistair Francis
2023-05-07 22:22 ` Alistair Francis
2023-05-10 17:17 ` Michael Tokarev
2023-05-05 1:01 ` [PULL 20/89] target/riscv: Remove redundant call to riscv_cpu_virt_enabled Alistair Francis
2023-05-05 1:01 ` [PULL 21/89] target/riscv: Remove redundant check on RVH Alistair Francis
2023-05-05 1:01 ` [PULL 22/89] target/riscv: Remove check on RVH for riscv_cpu_virt_enabled Alistair Francis
2023-05-05 1:01 ` [PULL 23/89] target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabled Alistair Francis
2023-05-05 1:01 ` [PULL 24/89] target/riscv: Convert env->virt to a bool env->virt_enabled Alistair Francis
2023-05-05 1:01 ` [PULL 25/89] target/riscv: Remove redundant parentheses Alistair Francis
2023-05-05 1:01 ` [PULL 26/89] target/riscv: Fix addr type for get_physical_address Alistair Francis
2023-05-05 1:01 ` [PULL 27/89] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault Alistair Francis
2023-05-05 1:01 ` [PULL 28/89] target/riscv: Remove riscv_cpu_virt_enabled() Alistair Francis
2023-05-05 1:01 ` [PULL 29/89] target/riscv: Fix format for indentation Alistair Francis
2023-05-05 1:01 ` [PULL 30/89] target/riscv: Fix format for comments Alistair Francis
2023-05-05 1:01 ` [PULL 31/89] target/riscv: Fix lines with over 80 characters Alistair Francis
2023-05-05 1:01 ` [PULL 32/89] hw/riscv: Add signature dump function for spike to run ACT tests Alistair Francis
2023-05-05 1:01 ` [PULL 33/89] target/riscv: sync env->misa_ext* with cpu->cfg in realize() Alistair Francis
2023-05-05 1:01 ` [PULL 34/89] target/riscv: remove MISA properties from isa_edata_arr[] Alistair Francis
2023-05-05 1:01 ` [PULL 35/89] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data Alistair Francis
2023-05-05 1:01 ` [PULL 36/89] target/riscv: introduce riscv_cpu_add_misa_properties() Alistair Francis
2023-05-05 1:01 ` [PULL 37/89] target/riscv: remove cpu->cfg.ext_a Alistair Francis
2023-05-05 1:01 ` [PULL 38/89] target/riscv: remove cpu->cfg.ext_c Alistair Francis
2023-05-05 1:01 ` [PULL 39/89] target/riscv: remove cpu->cfg.ext_d Alistair Francis
2023-05-05 1:01 ` [PULL 40/89] target/riscv: remove cpu->cfg.ext_f Alistair Francis
2023-05-05 1:01 ` [PULL 41/89] target/riscv: remove cpu->cfg.ext_i Alistair Francis
2023-05-05 1:01 ` [PULL 42/89] target/riscv: remove cpu->cfg.ext_e Alistair Francis
2023-05-05 1:01 ` [PULL 43/89] target/riscv: remove cpu->cfg.ext_m Alistair Francis
2023-05-05 1:01 ` [PULL 44/89] target/riscv: remove cpu->cfg.ext_s Alistair Francis
2023-05-05 1:01 ` [PULL 45/89] target/riscv: remove cpu->cfg.ext_u Alistair Francis
2023-05-05 1:01 ` [PULL 46/89] target/riscv: remove cpu->cfg.ext_h Alistair Francis
2023-05-05 1:01 ` [PULL 47/89] target/riscv: remove cpu->cfg.ext_j Alistair Francis
2023-05-05 1:02 ` [PULL 48/89] target/riscv: remove cpu->cfg.ext_v Alistair Francis
2023-05-05 1:02 ` [PULL 49/89] target/riscv: remove riscv_cpu_sync_misa_cfg() Alistair Francis
2023-05-05 1:02 ` [PULL 50/89] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() Alistair Francis
2023-05-05 1:02 ` [PULL 51/89] target/riscv: add RVG and remove cpu->cfg.ext_g Alistair Francis
2023-05-05 1:02 ` [PULL 52/89] target/riscv/cpu.c: redesign register_cpu_props() Alistair Francis
2023-05-05 1:02 ` [PULL 53/89] target/riscv: Fix the mstatus.MPP value after executing MRET Alistair Francis
2023-05-05 1:02 ` [PULL 54/89] target/riscv: Use PRV_RESERVED instead of PRV_H Alistair Francis
2023-05-05 1:02 ` [PULL 55/89] target/riscv: Legalize MPP value in write_mstatus Alistair Francis
2023-05-05 1:02 ` [PULL 56/89] target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx Alistair Francis
2023-05-05 1:02 ` [PULL 57/89] target/riscv: fix H extension TVM trap Alistair Francis
2023-05-05 1:02 ` [PULL 58/89] target/riscv: Extract virt enabled state from tb flags Alistair Francis
2023-05-05 1:02 ` [PULL 59/89] target/riscv: Add a general status enum for extensions Alistair Francis
2023-05-05 1:02 ` [PULL 60/89] target/riscv: Encode the FS and VS on a normal way for tb flags Alistair Francis
2023-05-05 1:02 ` [PULL 61/89] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Alistair Francis
2023-05-05 1:02 ` [PULL 62/89] target/riscv: Add a tb flags field for vstart Alistair Francis
2023-05-05 1:02 ` [PULL 63/89] target/riscv: Separate priv from mmu_idx Alistair Francis
2023-05-05 1:02 ` [PULL 64/89] target/riscv: Reduce overhead of MSTATUS_SUM change Alistair Francis
2023-05-05 1:02 ` [PULL 65/89] target/riscv: Use cpu_ld*_code_mmu for HLVX Alistair Francis
2023-05-05 1:02 ` [PULL 66/89] target/riscv: Handle HLV, HSV via helpers Alistair Francis
2023-05-05 1:02 ` [PULL 67/89] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Alistair Francis
2023-05-05 1:02 ` [PULL 68/89] target/riscv: Introduce mmuidx_sum Alistair Francis
2023-05-05 1:02 ` [PULL 69/89] target/riscv: Introduce mmuidx_priv Alistair Francis
2023-05-05 1:02 ` [PULL 70/89] target/riscv: Introduce mmuidx_2stage Alistair Francis
2023-05-05 1:02 ` [PULL 71/89] target/riscv: Move hstatus.spvp check to check_access_hlsv Alistair Francis
2023-05-05 1:02 ` [PULL 72/89] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Alistair Francis
2023-05-05 1:02 ` [PULL 73/89] target/riscv: Check SUM in the correct register Alistair Francis
2023-05-05 1:02 ` [PULL 74/89] target/riscv: Hoist second stage mode change to callers Alistair Francis
2023-05-05 1:02 ` [PULL 75/89] target/riscv: Hoist pbmte and hade out of the level loop Alistair Francis
2023-05-05 1:02 ` [PULL 76/89] target/riscv: Move leaf pte processing out of " Alistair Francis
2023-05-05 1:02 ` [PULL 77/89] target/riscv: Suppress pte update with is_debug Alistair Francis
2023-05-05 1:02 ` [PULL 78/89] target/riscv: Don't modify SUM " Alistair Francis
2023-05-05 1:02 ` [PULL 79/89] target/riscv: Merge checks for reserved pte flags Alistair Francis
2023-05-05 1:02 ` [PULL 80/89] target/riscv: Reorg access check in get_physical_address Alistair Francis
2023-05-05 1:02 ` [PULL 81/89] target/riscv: Reorg sum " Alistair Francis
2023-05-05 1:02 ` [PULL 82/89] hw/intc/riscv_aplic: Zero init APLIC internal state Alistair Francis
2023-05-05 1:02 ` [PULL 83/89] target/riscv: add CPU QOM header Alistair Francis
2023-05-05 1:02 ` [PULL 84/89] target/riscv: add query-cpy-definitions support Alistair Francis
2023-05-05 1:02 ` [PULL 85/89] target/riscv: add TYPE_RISCV_DYNAMIC_CPU Alistair Francis
2023-05-05 1:02 ` [PULL 86/89] target/riscv: Restore the predicate() NULL check behavior Alistair Francis
2023-05-07 22:21 ` Alistair Francis
2023-05-10 17:18 ` Michael Tokarev
2023-05-05 1:02 ` [PULL 87/89] target/riscv: Fix Guest Physical Address Translation Alistair Francis
2023-05-05 1:02 ` [PULL 88/89] riscv: Make sure an exception is raised if a pte is malformed Alistair Francis
2023-05-05 1:02 ` [PULL 89/89] target/riscv: add Ventana's Veyron V1 CPU Alistair Francis
2023-05-05 1:05 ` [PULL 00/89] riscv-to-apply queue Alistair Francis
2023-05-05 1:08 ` Alistair Francis
2023-05-05 15:00 ` Richard Henderson
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