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From: Rajnesh Kanwal <rkanwal@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, liweiwei@iscas.ac.cn,
	dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com,
	atishp@rivosinc.com, apatel@ventanamicro.com,
	Rajnesh Kanwal <rkanwal@rivosinc.com>
Subject: [PATCH 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie.
Date: Thu, 18 May 2023 12:38:33 +0100	[thread overview]
Message-ID: <20230518113838.130084-2-rkanwal@rivosinc.com> (raw)
In-Reply-To: <20230518113838.130084-1-rkanwal@rivosinc.com>

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4451bd1263..041f0b3e2e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1522,7 +1522,7 @@ static RISCVException rmw_mie64(CPURISCVState *env, int csrno,
     env->mie = (env->mie & ~mask) | (new_val & mask);
 
     if (!riscv_has_ext(env, RVH)) {
-        env->mie &= ~((uint64_t)MIP_SGEIP);
+        env->mie &= ~((uint64_t)HS_MODE_INTERRUPTS);
     }
 
     return RISCV_EXCP_NONE;
-- 
2.25.1



  reply	other threads:[~2023-05-18 14:09 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-18 11:38 [PATCH 0/6] Add RISC-V Virtual IRQs and IRQ filtering support Rajnesh Kanwal
2023-05-18 11:38 ` Rajnesh Kanwal [this message]
2023-05-18 11:38 ` [PATCH 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST Rajnesh Kanwal
2023-05-18 15:20   ` Loïc Lefort
2023-05-18 15:47     ` Rajnesh Kanwal
2023-05-18 11:38 ` [PATCH 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled Rajnesh Kanwal
2023-05-22 16:43   ` Daniel Henrique Barboza
2023-05-18 11:38 ` [PATCH 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip Rajnesh Kanwal
2023-05-18 11:38 ` [PATCH 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support Rajnesh Kanwal
2023-05-18 11:38 ` [PATCH 6/6] target/riscv: Add HS-mode " Rajnesh Kanwal
2023-05-22 17:18   ` Daniel Henrique Barboza
2023-05-26 16:30     ` Rajnesh Kanwal

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