From: Rajnesh Kanwal <rkanwal@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, liweiwei@iscas.ac.cn,
dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com,
atishp@rivosinc.com, apatel@ventanamicro.com,
Rajnesh Kanwal <rkanwal@rivosinc.com>
Subject: [PATCH 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.
Date: Thu, 18 May 2023 12:38:34 +0100 [thread overview]
Message-ID: <20230518113838.130084-3-rkanwal@rivosinc.com> (raw)
In-Reply-To: <20230518113838.130084-1-rkanwal@rivosinc.com>
RISCV_EXCP_SEMIHOST is set to 0x10, which can also be a local
interrupt as well. This change adds a check for async flag
before invoking semihosting logic.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 57d04385f1..c78a2a9514 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1602,7 +1602,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
target_ulong htval = 0;
target_ulong mtval2 = 0;
- if (cause == RISCV_EXCP_SEMIHOST) {
+ if (!async && cause == RISCV_EXCP_SEMIHOST) {
do_common_semihosting(cs);
env->pc += 4;
return;
--
2.25.1
next prev parent reply other threads:[~2023-05-18 13:37 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-18 11:38 [PATCH 0/6] Add RISC-V Virtual IRQs and IRQ filtering support Rajnesh Kanwal
2023-05-18 11:38 ` [PATCH 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie Rajnesh Kanwal
2023-05-18 11:38 ` Rajnesh Kanwal [this message]
2023-05-18 15:20 ` [PATCH 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST Loïc Lefort
2023-05-18 15:47 ` Rajnesh Kanwal
2023-05-18 11:38 ` [PATCH 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled Rajnesh Kanwal
2023-05-22 16:43 ` Daniel Henrique Barboza
2023-05-18 11:38 ` [PATCH 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip Rajnesh Kanwal
2023-05-18 11:38 ` [PATCH 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support Rajnesh Kanwal
2023-05-18 11:38 ` [PATCH 6/6] target/riscv: Add HS-mode " Rajnesh Kanwal
2023-05-22 17:18 ` Daniel Henrique Barboza
2023-05-26 16:30 ` Rajnesh Kanwal
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