From: Andrew Jones <ajones@ventanamicro.com>
To: Tommy Wu <tommy.wu@sifive.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
frank.chang@sifive.com, palmer@dabbelt.com,
alistair.francis@wdc.com, bin.meng@windriver.com,
liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org
Subject: Re: [PATCH v4 0/4] target/riscv: Add Smrnmi support.
Date: Thu, 8 Jun 2023 11:43:34 +0200 [thread overview]
Message-ID: <20230608-01a21738d16a20808eceb795@orel> (raw)
In-Reply-To: <20230608072314.3561109-1-tommy.wu@sifive.com>
On Thu, Jun 08, 2023 at 12:23:10AM -0700, Tommy Wu wrote:
> This patchset added support for Smrnmi Extension in RISC-V.
>
> There are four new CSRs and one new instruction added to allow NMI to be
> resumable in RISC-V, which are:
>
> =============================================================
> * mnscratch (0x740)
> * mnepc (0x741)
> * mncause (0x742)
> * mnstatus (0x744)
> =============================================================
> * mnret: To return from RNMI interrupt/exception handler.
> =============================================================
>
> RNMI also has higher priority than any other interrupts or exceptions
> and cannot be disabled by software.
>
> RNMI may be used to route to other devices such as Bus Error Unit or
> Watchdog Timer in the future.
>
> The interrupt/exception trap handler addresses of RNMI are
> implementation defined.
Is there an M-mode software PoC for this with implemented handlers?
Thanks,
drew
>
> Changelog:
>
> v4
> * Fix some coding style issues.
> ( Thank Daniel for the suggestions. )
>
> v3
> * Update to the newest version of Smrnmi extension specification.
>
> v2
> * split up the series into more commits for convenience of review.
> * add missing rnmi_irqvec and rnmi_excpvec properties to riscv_harts.
>
> Tommy Wu (4):
> target/riscv: Add Smrnmi cpu extension.
> target/riscv: Add Smrnmi CSRs.
> target/riscv: Handle Smrnmi interrupt and exception.
> target/riscv: Add Smrnmi mnret instruction.
>
> hw/riscv/riscv_hart.c | 21 +++++
> include/hw/riscv/riscv_hart.h | 4 +
> target/riscv/cpu.c | 18 ++++
> target/riscv/cpu.h | 11 +++
> target/riscv/cpu_bits.h | 23 ++++++
> target/riscv/cpu_helper.c | 81 ++++++++++++++++--
> target/riscv/csr.c | 82 +++++++++++++++++++
> target/riscv/helper.h | 1 +
> target/riscv/insn32.decode | 3 +
> .../riscv/insn_trans/trans_privileged.c.inc | 12 +++
> target/riscv/op_helper.c | 49 +++++++++++
> 11 files changed, 300 insertions(+), 5 deletions(-)
>
> --
> 2.31.1
>
>
prev parent reply other threads:[~2023-06-08 9:43 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-08 7:23 [PATCH v4 0/4] target/riscv: Add Smrnmi support Tommy Wu
2023-06-08 7:23 ` [PATCH v4 1/4] target/riscv: Add Smrnmi cpu extension Tommy Wu
2023-06-08 9:52 ` Andrew Jones
2023-06-12 5:03 ` Alistair Francis
2023-06-08 7:23 ` [PATCH v4 2/4] target/riscv: Add Smrnmi CSRs Tommy Wu
2023-06-12 4:58 ` Alistair Francis
2023-06-08 7:23 ` [PATCH v4 3/4] target/riscv: Handle Smrnmi interrupt and exception Tommy Wu
2023-06-08 7:23 ` [PATCH v4 4/4] target/riscv: Add Smrnmi mnret instruction Tommy Wu
2023-06-08 9:43 ` Andrew Jones [this message]
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