* [PATCH] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
@ 2023-08-29 21:50 leon
2023-09-01 15:00 ` mchitale
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: leon @ 2023-08-29 21:50 UTC (permalink / raw)
To: qemu-riscv, qemu-devel; +Cc: Alistair Francis, Leon Schuermann
From: Leon Schuermann <leons@opentitan.org>
When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP
configuration lock bits must not apply. While this behavior is
implemented for the pmpcfgX CSRs, this bit is not respected for
changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
writes work even on locked regions when the global rule-lock bypass is
enabled.
Signed-off-by: Leon Schuermann <leons@opentitan.org>
---
target/riscv/pmp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 9d8db493e6..5e60c26031 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -44,6 +44,10 @@ static inline uint8_t pmp_get_a_field(uint8_t cfg)
*/
static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
{
+ /* mseccfg.RLB is set */
+ if (MSECCFG_RLB_ISSET(env)) {
+ return 0;
+ }
if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
return 1;
base-commit: a8fc5165aab02f328ccd148aafec1e59fd1426eb
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
2023-08-29 21:50 [PATCH] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes leon
@ 2023-09-01 15:00 ` mchitale
2023-09-04 1:00 ` Alistair Francis
2023-09-04 1:05 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: mchitale @ 2023-09-01 15:00 UTC (permalink / raw)
To: leon, qemu-riscv, qemu-devel; +Cc: Alistair Francis, Leon Schuermann
On Tue, 2023-08-29 at 17:50 -0400, leon@is.currently.online wrote:
> From: Leon Schuermann <leons@opentitan.org>
>
> When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the
> PMP
> configuration lock bits must not apply. While this behavior is
> implemented for the pmpcfgX CSRs, this bit is not respected for
> changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
> writes work even on locked regions when the global rule-lock bypass
> is
> enabled.
>
> Signed-off-by: Leon Schuermann <leons@opentitan.org>
> ---
> target/riscv/pmp.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 9d8db493e6..5e60c26031 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -44,6 +44,10 @@ static inline uint8_t pmp_get_a_field(uint8_t cfg)
> */
> static inline int pmp_is_locked(CPURISCVState *env, uint32_t
> pmp_index)
> {
> + /* mseccfg.RLB is set */
> + if (MSECCFG_RLB_ISSET(env)) {
> + return 0;
> + }
>
> if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
> return 1;
>
> base-commit: a8fc5165aab02f328ccd148aafec1e59fd1426eb
Reviewed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
2023-08-29 21:50 [PATCH] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes leon
2023-09-01 15:00 ` mchitale
@ 2023-09-04 1:00 ` Alistair Francis
2023-09-04 1:05 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2023-09-04 1:00 UTC (permalink / raw)
To: leon; +Cc: qemu-riscv, qemu-devel, Leon Schuermann
On Wed, Aug 30, 2023 at 7:50 AM <leon@is.currently.online> wrote:
>
> From: Leon Schuermann <leons@opentitan.org>
>
> When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP
> configuration lock bits must not apply. While this behavior is
> implemented for the pmpcfgX CSRs, this bit is not respected for
> changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
> writes work even on locked regions when the global rule-lock bypass is
> enabled.
>
> Signed-off-by: Leon Schuermann <leons@opentitan.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/pmp.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 9d8db493e6..5e60c26031 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -44,6 +44,10 @@ static inline uint8_t pmp_get_a_field(uint8_t cfg)
> */
> static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
> {
> + /* mseccfg.RLB is set */
> + if (MSECCFG_RLB_ISSET(env)) {
> + return 0;
> + }
>
> if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
> return 1;
>
> base-commit: a8fc5165aab02f328ccd148aafec1e59fd1426eb
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
2023-08-29 21:50 [PATCH] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes leon
2023-09-01 15:00 ` mchitale
2023-09-04 1:00 ` Alistair Francis
@ 2023-09-04 1:05 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2023-09-04 1:05 UTC (permalink / raw)
To: leon; +Cc: qemu-riscv, qemu-devel, Leon Schuermann
On Wed, Aug 30, 2023 at 7:50 AM <leon@is.currently.online> wrote:
>
> From: Leon Schuermann <leons@opentitan.org>
>
> When the rule-lock bypass (RLB) bit is set in the mseccfg CSR, the PMP
> configuration lock bits must not apply. While this behavior is
> implemented for the pmpcfgX CSRs, this bit is not respected for
> changes to the pmpaddrX CSRs. This patch ensures that pmpaddrX CSR
> writes work even on locked regions when the global rule-lock bypass is
> enabled.
>
> Signed-off-by: Leon Schuermann <leons@opentitan.org>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/pmp.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 9d8db493e6..5e60c26031 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -44,6 +44,10 @@ static inline uint8_t pmp_get_a_field(uint8_t cfg)
> */
> static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
> {
> + /* mseccfg.RLB is set */
> + if (MSECCFG_RLB_ISSET(env)) {
> + return 0;
> + }
>
> if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) {
> return 1;
>
> base-commit: a8fc5165aab02f328ccd148aafec1e59fd1426eb
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2023-08-29 21:50 [PATCH] target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes leon
2023-09-01 15:00 ` mchitale
2023-09-04 1:00 ` Alistair Francis
2023-09-04 1:05 ` Alistair Francis
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