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From: Alvin Chang via <qemu-devel@nongnu.org>
To: <qemu-riscv@nongnu.org>, <qemu-devel@nongnu.org>
Cc: <alistair.francis@wdc.com>, <bin.meng@windriver.com>,
	<liwei1518@gmail.com>, <dbarboza@ventanamicro.com>,
	<zhiwei_liu@linux.alibaba.com>,
	Alvin Chang <alvinga@andestech.com>
Subject: [PATCH 2/4] target/riscv: Apply modularized matching conditions for breakpoint
Date: Mon, 19 Feb 2024 11:25:57 +0800	[thread overview]
Message-ID: <20240219032559.79665-3-alvinga@andestech.com> (raw)
In-Reply-To: <20240219032559.79665-1-alvinga@andestech.com>

We have implemented trigger_common_match(), which checks if the enabled
privilege levels of the trigger match CPU's current privilege level.
Remove the related code in riscv_cpu_debug_check_breakpoint() and invoke
trigger_common_match() to check the privilege levels of the type 2 and
type 6 triggers for the breakpoints.

Only the execution bit and the executed PC should be futher checked in
riscv_cpu_debug_check_breakpoint().

Signed-off-by: Alvin Chang <alvinga@andestech.com>
---
 target/riscv/debug.c | 26 ++++++--------------------
 1 file changed, 6 insertions(+), 20 deletions(-)

diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 7932233073..b971ed5d7a 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -855,21 +855,17 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
         for (i = 0; i < RV_MAX_TRIGGERS; i++) {
             trigger_type = get_trigger_type(env, i);
 
+            if (!trigger_common_match(env, trigger_type, i)) {
+                continue;
+            }
+
             switch (trigger_type) {
             case TRIGGER_TYPE_AD_MATCH:
-                /* type 2 trigger cannot be fired in VU/VS mode */
-                if (env->virt_enabled) {
-                    return false;
-                }
-
                 ctrl = env->tdata1[i];
                 pc = env->tdata2[i];
 
                 if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
-                    /* check U/S/M bit against current privilege level */
-                    if ((ctrl >> 3) & BIT(env->priv)) {
-                        return true;
-                    }
+                    return true;
                 }
                 break;
             case TRIGGER_TYPE_AD_MATCH6:
@@ -877,17 +873,7 @@ bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
                 pc = env->tdata2[i];
 
                 if ((ctrl & TYPE6_EXEC) && (bp->pc == pc)) {
-                    if (env->virt_enabled) {
-                        /* check VU/VS bit against current privilege level */
-                        if ((ctrl >> 23) & BIT(env->priv)) {
-                            return true;
-                        }
-                    } else {
-                        /* check U/S/M bit against current privilege level */
-                        if ((ctrl >> 3) & BIT(env->priv)) {
-                            return true;
-                        }
-                    }
+                    return true;
                 }
                 break;
             default:
-- 
2.34.1



  parent reply	other threads:[~2024-02-19  3:27 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-19  3:25 [PATCH 0/4] RISC-V: Modularize common match conditions for trigger Alvin Chang via
2024-02-19  3:25 ` [PATCH 1/4] target/riscv: Add functions for common matching conditions of trigger Alvin Chang via
2024-02-21 17:09   ` Daniel Henrique Barboza
2024-02-19  3:25 ` Alvin Chang via [this message]
2024-02-21 17:25   ` [PATCH 2/4] target/riscv: Apply modularized matching conditions for breakpoint Daniel Henrique Barboza
2024-02-22  1:46     ` Alvin Che-Chia Chang(張哲嘉)
2024-02-22 12:37       ` Daniel Henrique Barboza
2024-02-19  3:25 ` [PATCH 3/4] target/riscv: Apply modularized matching conditions for watchpoint Alvin Chang via
2024-02-21 17:31   ` Daniel Henrique Barboza
2024-02-19  3:25 ` [PATCH 4/4] target/riscv: Apply modularized matching conditions for icount trigger Alvin Chang via
2024-02-21 18:05   ` Daniel Henrique Barboza
2024-02-22  2:05     ` Alvin Che-Chia Chang(張哲嘉)

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