From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Alvin Chang <alvinga@andestech.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, bin.meng@windriver.com,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com
Subject: Re: [PATCH 3/4] target/riscv: Apply modularized matching conditions for watchpoint
Date: Wed, 21 Feb 2024 14:31:18 -0300 [thread overview]
Message-ID: <ec025245-ed62-4c8b-8110-0eb996280bde@ventanamicro.com> (raw)
In-Reply-To: <20240219032559.79665-4-alvinga@andestech.com>
On 2/19/24 00:25, Alvin Chang wrote:
> We have implemented trigger_common_match(), which checks if the enabled
> privilege levels of the trigger match CPU's current privilege level.
> Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke
> trigger_common_match() to check the privilege levels of the type 2 and
> type 6 triggers for the watchpoints.
>
> Only load/store bits and loaded/stored address should be further checked
> in riscv_cpu_debug_check_watchpoint().
>
> Signed-off-by: Alvin Chang <alvinga@andestech.com>
> ---
> target/riscv/debug.c | 26 ++++++--------------------
> 1 file changed, 6 insertions(+), 20 deletions(-)
>
> diff --git a/target/riscv/debug.c b/target/riscv/debug.c
> index b971ed5d7a..67ba19c966 100644
> --- a/target/riscv/debug.c
> +++ b/target/riscv/debug.c
> @@ -899,13 +899,12 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
> for (i = 0; i < RV_MAX_TRIGGERS; i++) {
> trigger_type = get_trigger_type(env, i);
>
> + if (!trigger_common_match(env, trigger_type, i)) {
> + continue;
> + }
> +
The same comments I made in patch 2 also applies here. It's ok to change
how the function behaves as long as we're doing it on purpose and explaining
why in the commit message. Otherwise this if (!trigger_common_match()"
conditional should "return false" instead of keep looping to maintain
the existing behavior.
Thanks,
Daniel
> switch (trigger_type) {
> case TRIGGER_TYPE_AD_MATCH:
> - /* type 2 trigger cannot be fired in VU/VS mode */
> - if (env->virt_enabled) {
> - return false;
> - }
> -
> ctrl = env->tdata1[i];
> addr = env->tdata2[i];
> flags = 0;
> @@ -918,10 +917,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
> }
>
> if ((wp->flags & flags) && (wp->vaddr == addr)) {
> - /* check U/S/M bit against current privilege level */
> - if ((ctrl >> 3) & BIT(env->priv)) {
> - return true;
> - }
> + return true;
> }
> break;
> case TRIGGER_TYPE_AD_MATCH6:
> @@ -937,17 +933,7 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
> }
>
> if ((wp->flags & flags) && (wp->vaddr == addr)) {
> - if (env->virt_enabled) {
> - /* check VU/VS bit against current privilege level */
> - if ((ctrl >> 23) & BIT(env->priv)) {
> - return true;
> - }
> - } else {
> - /* check U/S/M bit against current privilege level */
> - if ((ctrl >> 3) & BIT(env->priv)) {
> - return true;
> - }
> - }
> + return true;
> }
> break;
> default:
next prev parent reply other threads:[~2024-02-21 17:31 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-19 3:25 [PATCH 0/4] RISC-V: Modularize common match conditions for trigger Alvin Chang via
2024-02-19 3:25 ` [PATCH 1/4] target/riscv: Add functions for common matching conditions of trigger Alvin Chang via
2024-02-21 17:09 ` Daniel Henrique Barboza
2024-02-19 3:25 ` [PATCH 2/4] target/riscv: Apply modularized matching conditions for breakpoint Alvin Chang via
2024-02-21 17:25 ` Daniel Henrique Barboza
2024-02-22 1:46 ` Alvin Che-Chia Chang(張哲嘉)
2024-02-22 12:37 ` Daniel Henrique Barboza
2024-02-19 3:25 ` [PATCH 3/4] target/riscv: Apply modularized matching conditions for watchpoint Alvin Chang via
2024-02-21 17:31 ` Daniel Henrique Barboza [this message]
2024-02-19 3:25 ` [PATCH 4/4] target/riscv: Apply modularized matching conditions for icount trigger Alvin Chang via
2024-02-21 18:05 ` Daniel Henrique Barboza
2024-02-22 2:05 ` Alvin Che-Chia Chang(張哲嘉)
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