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From: David Hildenbrand <david@redhat.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: pbonzini@redhat.com, alex.bennee@linaro.org, stefanha@redhat.com
Subject: Re: [PATCH v3 01/20] exec: Use TARGET_PAGE_BITS_MIN for TLB flags
Date: Mon, 23 Sep 2019 10:24:56 +0200	[thread overview]
Message-ID: <460bd9c8-e2b6-0db9-2db0-392621e5e613@redhat.com> (raw)
In-Reply-To: <20190922035458.14879-2-richard.henderson@linaro.org>

On 22.09.19 05:54, Richard Henderson wrote:
> These bits do not need to vary with the actual page size
> used by the guest.
> 
> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  include/exec/cpu-all.h | 16 ++++++++++------
>  1 file changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
> index d2d443c4f9..e0c8dc540c 100644
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -317,20 +317,24 @@ CPUArchState *cpu_copy(CPUArchState *env);
>  
>  #if !defined(CONFIG_USER_ONLY)
>  
> -/* Flags stored in the low bits of the TLB virtual address.  These are
> - * defined so that fast path ram access is all zeros.
> +/*
> + * Flags stored in the low bits of the TLB virtual address.
> + * These are defined so that fast path ram access is all zeros.
>   * The flags all must be between TARGET_PAGE_BITS and
>   * maximum address alignment bit.
> + *
> + * Use TARGET_PAGE_BITS_MIN so that these bits are constant
> + * when TARGET_PAGE_BITS_VARY is in effect.
>   */
>  /* Zero if TLB entry is valid.  */
> -#define TLB_INVALID_MASK    (1 << (TARGET_PAGE_BITS - 1))
> +#define TLB_INVALID_MASK    (1 << (TARGET_PAGE_BITS_MIN - 1))
>  /* Set if TLB entry references a clean RAM page.  The iotlb entry will
>     contain the page physical address.  */
> -#define TLB_NOTDIRTY        (1 << (TARGET_PAGE_BITS - 2))
> +#define TLB_NOTDIRTY        (1 << (TARGET_PAGE_BITS_MIN - 2))
>  /* Set if TLB entry is an IO callback.  */
> -#define TLB_MMIO            (1 << (TARGET_PAGE_BITS - 3))
> +#define TLB_MMIO            (1 << (TARGET_PAGE_BITS_MIN - 3))
>  /* Set if TLB entry contains a watchpoint.  */
> -#define TLB_WATCHPOINT      (1 << (TARGET_PAGE_BITS - 4))
> +#define TLB_WATCHPOINT      (1 << (TARGET_PAGE_BITS_MIN - 4))
>  
>  /* Use this mask to check interception with an alignment mask
>   * in a TCG backend.
> 

Reviewed-by: David Hildenbrand <david@redhat.com>

-- 

Thanks,

David / dhildenb


  reply	other threads:[~2019-09-23  8:34 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-22  3:54 [PATCH v3 00/20] Move rom and notdirty handling to cputlb Richard Henderson
2019-09-22  3:54 ` [PATCH v3 01/20] exec: Use TARGET_PAGE_BITS_MIN for TLB flags Richard Henderson
2019-09-23  8:24   ` David Hildenbrand [this message]
2019-09-22  3:54 ` [PATCH v3 02/20] exec: Split out variable page size support to exec-vary.c Richard Henderson
2019-09-23  8:26   ` David Hildenbrand
2019-09-23 16:27     ` Richard Henderson
2019-09-22  3:54 ` [PATCH v3 03/20] exec: Use const alias for TARGET_PAGE_BITS_VARY Richard Henderson
2019-09-22  3:54 ` [PATCH v3 04/20] exec: Restrict TARGET_PAGE_BITS_VARY assert to CONFIG_DEBUG_TCG Richard Henderson
2019-09-22  3:54 ` [PATCH v3 05/20] exec: Promote TARGET_PAGE_MASK to target_long Richard Henderson
2019-09-23  8:30   ` David Hildenbrand
2019-09-22  3:54 ` [PATCH v3 06/20] exec: Tidy TARGET_PAGE_ALIGN Richard Henderson
2019-09-23  8:30   ` David Hildenbrand
2019-09-22  3:54 ` [PATCH v3 07/20] exec: Cache TARGET_PAGE_MASK for TARGET_PAGE_BITS_VARY Richard Henderson
2019-09-23  8:31   ` David Hildenbrand
2019-09-22  3:54 ` [PATCH v3 08/20] cputlb: Disable __always_inline__ without optimization Richard Henderson
2019-09-23  9:18   ` Philippe Mathieu-Daudé
2019-09-23  9:45   ` Paolo Bonzini
2019-09-23 16:00     ` Richard Henderson
2019-09-23 16:49       ` Paolo Bonzini
2019-09-23 18:09         ` Richard Henderson
2019-09-22  3:54 ` [PATCH v3 09/20] cputlb: Replace switches in load/store_helper with callback Richard Henderson
2019-09-23  8:32   ` David Hildenbrand
2019-09-23  9:27   ` Philippe Mathieu-Daudé
2019-09-23  9:51   ` Paolo Bonzini
2019-09-23  9:54     ` David Hildenbrand
2019-09-23 10:02       ` Paolo Bonzini
2019-09-23 15:52         ` Richard Henderson
2019-09-23 18:18           ` Richard Henderson
2019-09-22  3:54 ` [PATCH v3 10/20] cputlb: Introduce TLB_BSWAP Richard Henderson
2019-09-23  8:33   ` David Hildenbrand
2019-09-22  3:54 ` [PATCH v3 11/20] exec: Adjust notdirty tracing Richard Henderson
2019-09-23  9:17   ` Philippe Mathieu-Daudé
2019-09-22  3:54 ` [PATCH v3 12/20] cputlb: Move ROM handling from I/O path to TLB path Richard Henderson
2019-09-23  8:39   ` David Hildenbrand
2019-09-22  3:54 ` [PATCH v3 13/20] cputlb: Move NOTDIRTY " Richard Henderson
2019-09-23  8:41   ` David Hildenbrand
2019-09-23  9:30   ` Philippe Mathieu-Daudé
2019-09-22  3:54 ` [PATCH v3 14/20] cputlb: Partially inline memory_region_section_get_iotlb Richard Henderson
2019-09-22  3:54 ` [PATCH v3 15/20] cputlb: Merge and move memory_notdirty_write_{prepare, complete} Richard Henderson
2019-09-22  3:54 ` [PATCH v3 16/20] cputlb: Handle TLB_NOTDIRTY in probe_access Richard Henderson
2019-09-22  3:54 ` [PATCH v3 17/20] cputlb: Remove cpu->mem_io_vaddr Richard Henderson
2019-09-23  8:50   ` David Hildenbrand
2019-09-22  3:54 ` [PATCH v3 18/20] cputlb: Remove tb_invalidate_phys_page_range is_cpu_write_access Richard Henderson
2019-09-23  8:52   ` David Hildenbrand
2019-09-23 16:05     ` Richard Henderson
2019-09-23 16:50       ` Paolo Bonzini
2019-09-22  3:54 ` [PATCH v3 19/20] cputlb: Pass retaddr to tb_invalidate_phys_page_fast Richard Henderson
2019-09-23  8:53   ` David Hildenbrand
2019-09-22  3:54 ` [PATCH v3 20/20] cputlb: Pass retaddr to tb_check_watchpoint Richard Henderson
2019-09-23  8:54   ` David Hildenbrand
2019-09-22  4:02 ` [PATCH v3 00/20] Move rom and notdirty handling to cputlb Richard Henderson
2019-09-22  6:46 ` no-reply
2019-09-23  8:23 ` David Hildenbrand

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