From: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
To: "Cédric Le Goater" <clg@kaod.org>,
"Peter Maydell" <peter.maydell@linaro.org>
Cc: Andrew Jeffery <andrew@aj.id.au>, Thomas Huth <thuth@redhat.com>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org,
Joel Stanley <joel@jms.id.au>
Subject: Re: [PATCH 08/24] tests/qtest: Add test for Aspeed HACE
Date: Wed, 7 Apr 2021 16:33:04 -0300 [thread overview]
Message-ID: <96574978-a20e-2bb0-7b4d-77ae3327ce4c@linux.vnet.ibm.com> (raw)
In-Reply-To: <20210407171637.777743-9-clg@kaod.org>
On 4/7/2021 2:16 PM, Cédric Le Goater wrote:
> From: Joel Stanley <joel@jms.id.au>
>
> This adds a test for the Aspeed Hash and Crypto (HACE) engine. It tests
> the currently implemented behavior of the hash functionality.
>
> The tests are similar, but are cut/pasted instead of broken out into a
> common function so the assert machinery produces useful output when a
> test fails.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Acked-by: Thomas Huth <thuth@redhat.com>
> [ clg: - qtest_quit() fix ]
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> Message-Id: <20210324070955.125941-4-joel@jms.id.au>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
> ---
> tests/qtest/aspeed_hace-test.c | 321 +++++++++++++++++++++++++++++++++
> MAINTAINERS | 1 +
> tests/qtest/meson.build | 3 +
> 3 files changed, 325 insertions(+)
> create mode 100644 tests/qtest/aspeed_hace-test.c
>
> diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c
> new file mode 100644
> index 000000000000..675774e96eb9
> --- /dev/null
> +++ b/tests/qtest/aspeed_hace-test.c
> @@ -0,0 +1,321 @@
> +/*
> + * QTest testcase for the ASPEED Hash and Crypto Engine
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + * Copyright 2021 IBM Corp.
> + */
> +
> +#include "qemu/osdep.h"
> +
> +#include "libqos/libqtest.h"
> +#include "qemu-common.h"
> +#include "qemu/bitops.h"
> +
> +#define HACE_CMD 0x10
> +#define HACE_SHA_BE_EN BIT(3)
> +#define HACE_MD5_LE_EN BIT(2)
> +#define HACE_ALGO_MD5 0
> +#define HACE_ALGO_SHA1 BIT(5)
> +#define HACE_ALGO_SHA224 BIT(6)
> +#define HACE_ALGO_SHA256 (BIT(4) | BIT(6))
> +#define HACE_ALGO_SHA512 (BIT(5) | BIT(6))
> +#define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10))
> +#define HACE_SG_EN BIT(18)
> +
> +#define HACE_STS 0x1c
> +#define HACE_RSA_ISR BIT(13)
> +#define HACE_CRYPTO_ISR BIT(12)
> +#define HACE_HASH_ISR BIT(9)
> +#define HACE_RSA_BUSY BIT(2)
> +#define HACE_CRYPTO_BUSY BIT(1)
> +#define HACE_HASH_BUSY BIT(0)
> +#define HACE_HASH_SRC 0x20
> +#define HACE_HASH_DIGEST 0x24
> +#define HACE_HASH_KEY_BUFF 0x28
> +#define HACE_HASH_DATA_LEN 0x2c
> +#define HACE_HASH_CMD 0x30
> +
> +/*
> + * Test vector is the ascii "abc"
> + *
> + * Expected results were generated using command line utitiles:
> + *
> + * echo -n -e 'abc' | dd of=/tmp/test
> + * for hash in sha512sum sha256sum md5sum; do $hash /tmp/test; done
> + *
> + */
> +static const uint8_t test_vector[] = {0x61, 0x62, 0x63};
> +
> +static const uint8_t test_result_sha512[] = {
> + 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49,
> + 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2,
> + 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a,
> + 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd,
> + 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f,
> + 0xa5, 0x4c, 0xa4, 0x9f};
> +
> +static const uint8_t test_result_sha256[] = {
> + 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde,
> + 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c,
> + 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad};
> +
> +static const uint8_t test_result_md5[] = {
> + 0x90, 0x01, 0x50, 0x98, 0x3c, 0xd2, 0x4f, 0xb0, 0xd6, 0x96, 0x3f, 0x7d,
> + 0x28, 0xe1, 0x7f, 0x72};
> +
> +
> +static void write_regs(QTestState *s, uint32_t base, uint32_t src,
> + uint32_t length, uint32_t out, uint32_t method)
> +{
> + qtest_writel(s, base + HACE_HASH_SRC, src);
> + qtest_writel(s, base + HACE_HASH_DIGEST, out);
> + qtest_writel(s, base + HACE_HASH_DATA_LEN, length);
> + qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method);
> +}
> +
> +static void test_md5(const char *machine, const uint32_t base,
> + const uint32_t src_addr)
> +
> +{
> + QTestState *s = qtest_init(machine);
> +
> + uint32_t digest_addr = src_addr + 0x01000000;
> + uint8_t digest[16] = {0};
> +
> + /* Check engine is idle, no busy or irq bits set */
> + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0);
> +
> + /* Write test vector into memory */
> + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector));
> +
> + write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_MD5);
> +
> + /* Check hash IRQ status is asserted */
> + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200);
> +
> + /* Clear IRQ status and check status is deasserted */
> + qtest_writel(s, base + HACE_STS, 0x00000200);
> + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0);
> +
> + /* Read computed digest from memory */
> + qtest_memread(s, digest_addr, digest, sizeof(digest));
> +
> + /* Check result of computation */
> + g_assert_cmpmem(digest, sizeof(digest),
> + test_result_md5, sizeof(digest));
> +
> + qtest_quit(s);
> +}
> +
> +static void test_sha256(const char *machine, const uint32_t base,
> + const uint32_t src_addr)
> +{
> + QTestState *s = qtest_init(machine);
> +
> + const uint32_t digest_addr = src_addr + 0x1000000;
> + uint8_t digest[32] = {0};
> +
> + /* Check engine is idle, no busy or irq bits set */
> + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0);
> +
> + /* Write test vector into memory */
> + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector));
> +
> + write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_SHA256);
> +
> + /* Check hash IRQ status is asserted */
> + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200);
> +
> + /* Clear IRQ status and check status is deasserted */
> + qtest_writel(s, base + HACE_STS, 0x00000200);
> + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0);
> +
> + /* Read computed digest from memory */
> + qtest_memread(s, digest_addr, digest, sizeof(digest));
> +
> + /* Check result of computation */
> + g_assert_cmpmem(digest, sizeof(digest),
> + test_result_sha256, sizeof(digest));
> +
> + qtest_quit(s);
> +}
> +
> +static void test_sha512(const char *machine, const uint32_t base,
> + const uint32_t src_addr)
> +{
> + QTestState *s = qtest_init(machine);
> +
> + const uint32_t digest_addr = src_addr + 0x1000000;
> + uint8_t digest[64] = {0};
> +
> + /* Check engine is idle, no busy or irq bits set */
> + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0);
> +
> + /* Write test vector into memory */
> + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector));
> +
> + write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_SHA512);
> +
> + /* Check hash IRQ status is asserted */
> + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200);
> +
> + /* Clear IRQ status and check status is deasserted */
> + qtest_writel(s, base + HACE_STS, 0x00000200);
> + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0);
> +
> + /* Read computed digest from memory */
> + qtest_memread(s, digest_addr, digest, sizeof(digest));
> +
> + /* Check result of computation */
> + g_assert_cmpmem(digest, sizeof(digest),
> + test_result_sha512, sizeof(digest));
> +
> + qtest_quit(s);
> +}
> +
> +struct masks {
> + uint32_t src;
> + uint32_t dest;
> + uint32_t len;
> +};
> +
> +static const struct masks ast2600_masks = {
> + .src = 0x7fffffff,
> + .dest = 0x7ffffff8,
> + .len = 0x0fffffff,
> +};
> +
> +static const struct masks ast2500_masks = {
> + .src = 0x3fffffff,
> + .dest = 0x3ffffff8,
> + .len = 0x0fffffff,
> +};
> +
> +static const struct masks ast2400_masks = {
> + .src = 0x0fffffff,
> + .dest = 0x0ffffff8,
> + .len = 0x0fffffff,
> +};
> +
> +static void test_addresses(const char *machine, const uint32_t base,
> + const struct masks *expected)
> +{
> + QTestState *s = qtest_init(machine);
> +
> + /*
> + * Check command mode is zero, meaning engine is in direct access mode,
> + * as this affects the masking behavior of the HASH_SRC register.
> + */
> + g_assert_cmphex(qtest_readl(s, base + HACE_CMD), ==, 0);
> + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0);
> + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0);
> + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0);
> +
> +
> + /* Check that the address masking is correct */
> + qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff);
> + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, expected->src);
> +
> + qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff);
> + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, expected->dest);
> +
> + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff);
> + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, expected->len);
> +
> + /* Reset to zero */
> + qtest_writel(s, base + HACE_HASH_SRC, 0);
> + qtest_writel(s, base + HACE_HASH_DIGEST, 0);
> + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0);
> +
> + /* Check that all bits are now zero */
> + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0);
> + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0);
> + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0);
> +
> + qtest_quit(s);
> +}
> +
> +/* ast2600 */
> +static void test_md5_ast2600(void)
> +{
> + test_md5("-machine ast2600-evb", 0x1e6d0000, 0x80000000);
> +}
> +
> +static void test_sha256_ast2600(void)
> +{
> + test_sha256("-machine ast2600-evb", 0x1e6d0000, 0x80000000);
> +}
> +
> +static void test_sha512_ast2600(void)
> +{
> + test_sha512("-machine ast2600-evb", 0x1e6d0000, 0x80000000);
> +}
> +
> +static void test_addresses_ast2600(void)
> +{
> + test_addresses("-machine ast2600-evb", 0x1e6d0000, &ast2600_masks);
> +}
> +
> +/* ast2500 */
> +static void test_md5_ast2500(void)
> +{
> + test_md5("-machine ast2500-evb", 0x1e6e3000, 0x80000000);
> +}
> +
> +static void test_sha256_ast2500(void)
> +{
> + test_sha256("-machine ast2500-evb", 0x1e6e3000, 0x80000000);
> +}
> +
> +static void test_sha512_ast2500(void)
> +{
> + test_sha512("-machine ast2500-evb", 0x1e6e3000, 0x80000000);
> +}
> +
> +static void test_addresses_ast2500(void)
> +{
> + test_addresses("-machine ast2500-evb", 0x1e6e3000, &ast2500_masks);
> +}
> +
> +/* ast2400 */
> +static void test_md5_ast2400(void)
> +{
> + test_md5("-machine palmetto-bmc", 0x1e6e3000, 0x40000000);
> +}
> +
> +static void test_sha256_ast2400(void)
> +{
> + test_sha256("-machine palmetto-bmc", 0x1e6e3000, 0x40000000);
> +}
> +
> +static void test_sha512_ast2400(void)
> +{
> + test_sha512("-machine palmetto-bmc", 0x1e6e3000, 0x40000000);
> +}
> +
> +static void test_addresses_ast2400(void)
> +{
> + test_addresses("-machine palmetto-bmc", 0x1e6e3000, &ast2400_masks);
> +}
> +
> +int main(int argc, char **argv)
> +{
> + g_test_init(&argc, &argv, NULL);
> +
> + qtest_add_func("ast2600/hace/addresses", test_addresses_ast2600);
> + qtest_add_func("ast2600/hace/sha512", test_sha512_ast2600);
> + qtest_add_func("ast2600/hace/sha256", test_sha256_ast2600);
> + qtest_add_func("ast2600/hace/md5", test_md5_ast2600);
> +
> + qtest_add_func("ast2500/hace/addresses", test_addresses_ast2500);
> + qtest_add_func("ast2500/hace/sha512", test_sha512_ast2500);
> + qtest_add_func("ast2500/hace/sha256", test_sha256_ast2500);
> + qtest_add_func("ast2500/hace/md5", test_md5_ast2500);
> +
> + qtest_add_func("ast2400/hace/addresses", test_addresses_ast2400);
> + qtest_add_func("ast2400/hace/sha512", test_sha512_ast2400);
> + qtest_add_func("ast2400/hace/sha256", test_sha256_ast2400);
> + qtest_add_func("ast2400/hace/md5", test_md5_ast2400);
> +
> + return g_test_run();
> +}
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 58f342108e9e..63c050ddc84a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1026,6 +1026,7 @@ F: include/hw/misc/pca9552*.h
> F: hw/net/ftgmac100.c
> F: include/hw/net/ftgmac100.h
> F: docs/system/arm/aspeed.rst
> +F: tests/qtest/*aspeed*
>
> NRF51
> M: Joel Stanley <joel@jms.id.au>
> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
> index 902cfef7cb2f..84b3219c15c6 100644
> --- a/tests/qtest/meson.build
> +++ b/tests/qtest/meson.build
> @@ -163,12 +163,15 @@ qtests_npcm7xx = \
> 'npcm7xx_timer-test',
> 'npcm7xx_watchdog_timer-test'] + \
> (slirp.found() ? ['npcm7xx_emc-test'] : [])
> +qtests_aspeed = \
> + ['aspeed_hace-test']
> qtests_arm = \
> (config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \
> (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \
> (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \
> (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \
> (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \
> + (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed : []) + \
> (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
> ['arm-cpu-features',
> 'microbit-test',
>
--
Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com>
next prev parent reply other threads:[~2021-04-07 19:55 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-07 17:16 [PATCH 00/24] aspeed: fixes and extensions Cédric Le Goater
2021-04-07 17:16 ` [PATCH 01/24] aspeed/smc: Use the RAM memory region for DMAs Cédric Le Goater
2021-04-07 17:32 ` Philippe Mathieu-Daudé
2021-04-07 17:16 ` [PATCH 02/24] aspeed/smc: Remove unused "sdram-base" property Cédric Le Goater
2021-04-07 17:32 ` Philippe Mathieu-Daudé
2021-04-07 17:16 ` [PATCH 03/24] aspeed/i2c: Fix DMA address mask Cédric Le Goater
2021-04-07 21:22 ` Philippe Mathieu-Daudé
2021-04-08 8:58 ` Cédric Le Goater
2021-04-07 17:16 ` [PATCH 04/24] aspeed/i2c: Rename DMA address space Cédric Le Goater
2021-04-07 17:33 ` Philippe Mathieu-Daudé
2021-04-07 17:16 ` [PATCH 05/24] hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use alias Cédric Le Goater
2021-04-07 17:16 ` [PATCH 06/24] hw: Model ASPEED's Hash and Crypto Engine Cédric Le Goater
2021-04-07 19:31 ` Klaus Heinrich Kiwi
2021-04-07 17:16 ` [PATCH 07/24] aspeed: Integrate HACE Cédric Le Goater
2021-04-07 19:22 ` Klaus Heinrich Kiwi
2021-04-07 17:16 ` [PATCH 08/24] tests/qtest: Add test for Aspeed HACE Cédric Le Goater
2021-04-07 19:33 ` Klaus Heinrich Kiwi [this message]
2021-04-07 17:16 ` [PATCH 09/24] aspeed: Add Scater-Gather support for HACE Hash Cédric Le Goater
2021-04-08 12:39 ` Joel Stanley
2021-04-07 17:16 ` [PATCH 10/24] tests: Aspeed HACE Scatter-Gather tests Cédric Le Goater
2021-04-07 17:16 ` [PATCH 11/24] tests/acceptance: Test ast2400 and ast2500 machines Cédric Le Goater
2021-04-07 18:40 ` Willian Rampazzo
2021-04-07 17:16 ` [PATCH 12/24] tests/acceptance: Test ast2600 machine Cédric Le Goater
2021-04-07 18:36 ` Willian Rampazzo
2021-04-07 17:16 ` [PATCH 13/24] hw/misc/aspeed_xdma: Add AST2600 support Cédric Le Goater
2021-04-07 20:29 ` Eddie James
2021-04-07 17:16 ` [PATCH 14/24] aspeed/smc: Add a 'features' attribute to the object class Cédric Le Goater
2021-04-09 6:55 ` Joel Stanley
2021-04-07 17:16 ` [PATCH 15/24] aspeed/smc: Add extra controls to request DMA Cédric Le Goater
2021-04-09 6:54 ` Joel Stanley
2021-04-10 7:08 ` Cédric Le Goater
2021-04-07 17:16 ` [PATCH 16/24] tests/qtest: Rename m25p80 test in aspeed_smc test Cédric Le Goater
2021-04-09 6:55 ` Joel Stanley
2021-04-07 17:16 ` [PATCH 17/24] aspeed: Remove swift-bmc machine Cédric Le Goater
2021-04-07 18:13 ` Adriana Kobylak
2021-04-07 18:29 ` Peter Maydell
2021-04-08 7:40 ` Cédric Le Goater
2021-04-08 9:05 ` Peter Maydell
2021-04-07 17:16 ` [PATCH 18/24] aspeed: Add support for the rainier-bmc board Cédric Le Goater
2021-04-09 6:57 ` Joel Stanley
2021-04-07 17:16 ` [PATCH 19/24] hw/misc: Add an iBT device model Cédric Le Goater
2021-04-07 17:16 ` [PATCH 20/24] aspeed: Emulate the AST2600A3 Cédric Le Goater
2021-04-07 17:16 ` [PATCH 21/24] hw/block: m25p80: Add support for mt25qu02g Cédric Le Goater
2021-04-07 17:36 ` Alistair Francis
2021-04-08 8:00 ` Francisco Iglesias
2021-04-08 8:40 ` Cédric Le Goater
2021-04-08 9:21 ` Francisco Iglesias
2021-04-07 17:16 ` [PATCH 22/24] hw/misc: Add Infineon DPS310 sensor model Cédric Le Goater
2021-04-07 17:16 ` [PATCH 23/24] arm/aspeed: Add DPS310 to rainier Cédric Le Goater
2021-04-07 17:16 ` [PATCH 24/24] arm/aspeed: Add DPS310 to witherspoon Cédric Le Goater
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