From: Taylor Simpson <tsimpson@quicinc.com>
To: Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "ale@rev.ng" <ale@rev.ng>, Brian Cain <bcain@quicinc.com>,
"philmd@redhat.com" <philmd@redhat.com>
Subject: RE: [PATCH v2 17/21] Hexagon (target/hexagon) circular addressing
Date: Wed, 7 Apr 2021 03:11:30 +0000 [thread overview]
Message-ID: <BYAPR02MB48868074F14C421E3D07AEB4DE759@BYAPR02MB4886.namprd02.prod.outlook.com> (raw)
In-Reply-To: <365724a7-1013-e04a-43b1-dae87103fcd1@linaro.org>
> -----Original Message-----
> From: Richard Henderson <richard.henderson@linaro.org>
> Sent: Tuesday, April 6, 2021 5:12 PM
> To: Taylor Simpson <tsimpson@quicinc.com>; qemu-devel@nongnu.org
> Cc: philmd@redhat.com; ale@rev.ng; Brian Cain <bcain@quicinc.com>
> Subject: Re: [PATCH v2 17/21] Hexagon (target/hexagon) circular addressing
>
> On 3/31/21 8:53 PM, Taylor Simpson wrote:
> > +static inline TCGv gen_read_reg(TCGv result, int num)
>
> The unnecessary inlines are back, just after having removed them in patch 2.
The ones in genptr.c need to stay so we can switch between the overrides and helpers and eventually the idef-parser.
> > +#ifdef QEMU_GENERATE
> > +static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
> > +{
> > + /*
> > + * Section 2.2.4 of the Hexagon V67 Programmer's Reference Manual
> > + *
> > + * The "I" value from a modifier register is divided into two pieces
> > + * LSB bits 23:17
> > + * MSB bits 31:28
> > + * At the end we shift the result according to the shift argument
> > + */
> > + TCGv msb = tcg_temp_new();
> > + TCGv lsb = tcg_temp_new();
> > +
> > + tcg_gen_extract_tl(lsb, val, 17, 7);
> > + tcg_gen_extract_tl(msb, val, 28, 4);
> > + tcg_gen_movi_tl(result, 0);
> > + tcg_gen_deposit_tl(result, result, lsb, 0, 7);
> > + tcg_gen_deposit_tl(result, result, msb, 7, 4);
> > +
> > + tcg_gen_shli_tl(result, result, shift);
>
> This doesn't match
>
> > +#define fREAD_IREG(VAL) \
> > + (fSXTN(11, 64, (((VAL) & 0xf0000000) >> 21) | ((VAL >> 17) & 0x7f)))
>
> which has a sign-extension of the result.
>
> tcg_gen_extract_tl(lsb, val 17, 7);
> tcg_gen_sari_tl(msb, val, 21);
> tcg_gen_deposit_tl(result, msb, lsb, 0, 7);
Good catch - this is strange. The value gets passed to as the "M" argument to HELPER(fcircadd). The code there does
int32_t K_const = (M >> 24) & 0xf;
int32_t length = M & 0x1ffff;
I will consult with the architects on this.
Thanks,
Taylor
next prev parent reply other threads:[~2021-04-07 3:12 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-01 3:53 [PATCH v2 00/21] Hexagon (target/hexagon) update Taylor Simpson
2021-04-01 3:53 ` [PATCH v2 01/21] Hexagon (target/hexagon) TCG generation cleanup Taylor Simpson
2021-04-02 17:25 ` Richard Henderson
2021-04-02 17:46 ` Richard Henderson
2021-04-02 19:42 ` Taylor Simpson
2021-04-02 20:00 ` Richard Henderson
2021-04-01 3:53 ` [PATCH v2 02/21] Hexagon (target/hexagon) remove unnecessary inline directives Taylor Simpson
2021-04-02 17:26 ` Richard Henderson
2021-04-01 3:53 ` [PATCH v2 03/21] Hexagon (target/hexagon) use env_archcpu and env_cpu Taylor Simpson
2021-04-02 17:27 ` Richard Henderson
2021-04-01 3:53 ` [PATCH v2 04/21] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN Taylor Simpson
2021-04-02 17:34 ` Richard Henderson
2021-04-01 3:53 ` [PATCH v2 05/21] Hexagon (target/hexagon) decide if pred has been written at TCG gen time Taylor Simpson
2021-04-02 17:44 ` Richard Henderson
2021-04-01 3:53 ` [PATCH v2 06/21] Hexagon (target/hexagon) change variables from int to bool when appropriate Taylor Simpson
2021-04-01 3:53 ` [PATCH v2 07/21] Hexagon (target/hexagon) remove unused carry_from_add64 function Taylor Simpson
2021-04-01 3:53 ` [PATCH v2 08/21] Hexagon (target/hexagon) change type of softfloat_roundingmodes Taylor Simpson
2021-04-01 3:53 ` [PATCH v2 09/21] Hexagon (target/hexagon) use softfloat default NaN and tininess Taylor Simpson
2021-04-02 17:48 ` Richard Henderson
2021-04-01 3:53 ` [PATCH v2 10/21] Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn Taylor Simpson
2021-04-01 3:53 ` [PATCH v2 11/21] Hexagon (target/hexagon) use softfloat for float-to-int conversions Taylor Simpson
2021-04-06 20:09 ` Richard Henderson
2021-04-01 3:53 ` [PATCH v2 12/21] Hexagon (target/hexagon) add F2_sfrecipa instruction Taylor Simpson
2021-04-06 20:30 ` Richard Henderson
2021-04-06 20:46 ` Richard Henderson
2021-04-06 21:55 ` Taylor Simpson
2021-04-06 22:13 ` Richard Henderson
2021-04-01 3:53 ` [PATCH v2 13/21] Hexagon (target/hexagon) add F2_sfinvsqrta Taylor Simpson
2021-04-06 20:47 ` Richard Henderson
2021-04-01 3:53 ` [PATCH v2 14/21] Hexagon (target/hexagon) add A5_ACS (vacsh) Taylor Simpson
2021-04-06 20:51 ` Richard Henderson
2021-04-06 21:31 ` Taylor Simpson
2021-04-01 3:53 ` [PATCH v2 15/21] Hexagon (target/hexagon) add A6_vminub_RdP Taylor Simpson
2021-04-06 20:57 ` Richard Henderson
2021-04-01 3:53 ` [PATCH v2 16/21] Hexagon (target/hexagon) add A4_addp_c/A4_subp_c Taylor Simpson
2021-04-06 21:11 ` Richard Henderson
2021-04-06 21:58 ` Taylor Simpson
2021-04-01 3:53 ` [PATCH v2 17/21] Hexagon (target/hexagon) circular addressing Taylor Simpson
2021-04-06 22:11 ` Richard Henderson
2021-04-07 3:11 ` Taylor Simpson [this message]
2021-04-07 16:27 ` Taylor Simpson
2021-04-01 3:53 ` [PATCH v2 18/21] Hexagon (target/hexagon) bit reverse (brev) addressing Taylor Simpson
2021-04-06 22:35 ` Richard Henderson
2021-04-01 3:53 ` [PATCH v2 19/21] Hexagon (target/hexagon) load and unpack bytes instructions Taylor Simpson
2021-04-06 22:46 ` Richard Henderson
2021-04-01 3:53 ` [PATCH v2 20/21] Hexagon (target/hexagon) load into shifted register instructions Taylor Simpson
2021-04-06 22:50 ` Richard Henderson
2021-04-01 3:53 ` [PATCH v2 21/21] Hexagon (target/hexagon) CABAC decode bin Taylor Simpson
2021-04-06 22:54 ` Richard Henderson
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