What is the "E10, E20_0 XXX" Flag means on arm port?

What is the "E10, E20_0 XXX" Flag means on arm port?

[tugouxp]

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Hi folks:


 I Know the arm prelidge level can be divieded into EL0, EL1, EL2 and EL3, but i am confused by the following  definition on qemu arm port.
 for example, why E10 are postfix with _0 and _1, what is this meansings?


 typedef enum ARMMMUIdx {

2879     /* 

2880     ¦* A-profile.

2881     ¦*/

2882     ARMMMUIdx_E10_0      =  0 | ARM_MMU_IDX_A,     

2883     ARMMMUIdx_E20_0      =  1 | ARM_MMU_IDX_A,     

2884        

2885     ARMMMUIdx_E10_1      =  2 | ARM_MMU_IDX_A,     

2886     ARMMMUIdx_E10_1_PAN  =  3 | ARM_MMU_IDX_A,

2887                     

2888     ARMMMUIdx_E2         =  4 | ARM_MMU_IDX_A,     

2889     ARMMMUIdx_E20_2      =  5 | ARM_MMU_IDX_A,     

2890     ARMMMUIdx_E20_2_PAN  =  6 | ARM_MMU_IDX_A,

2891        

2892     ARMMMUIdx_SE10_0     = 7 | ARM_MMU_IDX_A,

2893     ARMMMUIdx_SE10_1     = 8 | ARM_MMU_IDX_A,

2894     ARMMMUIdx_SE10_1_PAN = 9 | ARM_MMU_IDX_A,

2895     ARMMMUIdx_SE3        = 10 | ARM_MMU_IDX_A,     

2896        

2897     ARMMMUIdx_Stage2     = 11 | ARM_MMU_IDX_A,    

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Re: What is the "E10, E20_0 XXX" Flag means on arm port?

[Peter Maydell]

On Wed, 17 Jun 2020 at 13:54, tugouxp <13824125580@163.com> wrote:
>
> Hi folks:
>
>  I Know the arm prelidge level can be divieded into EL0, EL1, EL2 and EL3, but i am confused by the following  definition on qemu arm port.
>  for example, why E10 are postfix with _0 and _1, what is this meansings?

The meanings of the different MMU indexes are described
in the long comment immediately preceding this enum.
For instance, ARMMMUIdx_E10_0 is "NS EL0 EL1&0 stage 1+2"
and ARMMMUIdx_E10_1 is "NS EL1 EL1&0 stage 1+2". See
the comment for the discussion of why we have more of
these than there are architectural "translation regimes"
as described in the Arm ARM.

thanks
-- PMM