From: Alistair Francis <alistair23@gmail.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com, ajones@ventanamicro.com
Subject: Re: [PATCH v9 15/20] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update()
Date: Thu, 7 Sep 2023 14:06:03 +1000 [thread overview]
Message-ID: <CAKmqyKMqeHimLKt00RQEtZXi36XL7YLQ5dfNd-ObQZRDUS78Sg@mail.gmail.com> (raw)
In-Reply-To: <20230901194627.1214811-16-dbarboza@ventanamicro.com>
On Sat, Sep 2, 2023 at 5:49 AM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> During realize() time we're activating a lot of extensions based on some
> criteria, e.g.:
>
> if (cpu->cfg.ext_zk) {
> cpu->cfg.ext_zkn = true;
> cpu->cfg.ext_zkr = true;
> cpu->cfg.ext_zkt = true;
> }
>
> This practice resulted in at least one case where we ended up enabling
> something we shouldn't: RVC enabling zca/zcd/zcf when using a CPU that
> has priv_spec older than 1.12.0.
>
> We're also not considering user choice. There's no way of doing it now
> but this is about to change in the next few patches.
>
> cpu_cfg_ext_auto_update() will check for priv version mismatches before
> enabling extensions. If we have a mismatch between the current priv
> version and the extension we want to enable, do not enable it. In the
> near future, this same function will also consider user choice when
> deciding if we're going to enable/disable an extension or not.
>
> For now let's use it to handle zca/zcd/zcf enablement if RVC is enabled.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 43 ++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 40 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 43c68e1792..a4876df5f4 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -177,6 +177,43 @@ static void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset,
> *ext_enabled = en;
> }
>
> +static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> + if (isa_edata_arr[i].ext_enable_offset != ext_offset) {
> + continue;
> + }
> +
> + return isa_edata_arr[i].min_version;
> + }
> +
> + g_assert_not_reached();
> +}
> +
> +static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset,
> + bool value)
> +{
> + CPURISCVState *env = &cpu->env;
> + bool prev_val = isa_ext_is_enabled(cpu, ext_offset);
> + int min_version;
> +
> + if (prev_val == value) {
> + return;
> + }
> +
> + if (value && env->priv_ver != PRIV_VERSION_LATEST) {
> + /* Do not enable it if priv_ver is older than min_version */
> + min_version = cpu_cfg_ext_get_min_version(ext_offset);
> + if (env->priv_ver < min_version) {
> + return;
> + }
> + }
> +
> + isa_ext_update_enabled(cpu, ext_offset, value);
> +}
> +
> const char * const riscv_int_regnames[] = {
> "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
> "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
> @@ -1268,12 +1305,12 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
>
> /* zca, zcd and zcf has a PRIV 1.12.0 restriction */
> if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
> - cpu->cfg.ext_zca = true;
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
> - cpu->cfg.ext_zcf = true;
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
> }
> if (riscv_has_ext(env, RVD)) {
> - cpu->cfg.ext_zcd = true;
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
> }
> }
>
> --
> 2.41.0
>
>
next prev parent reply other threads:[~2023-09-07 4:07 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-01 19:46 [PATCH v9 00/20] riscv: 'max' CPU, detect user choice in TCG Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 01/20] target/riscv/cpu.c: split CPU options from riscv_cpu_extensions[] Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 02/20] target/riscv/cpu.c: skip 'bool' check when filtering KVM props Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 03/20] target/riscv/cpu.c: split kvm prop handling to its own helper Daniel Henrique Barboza
2023-09-11 13:32 ` Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 04/20] target/riscv: add DEFINE_PROP_END_OF_LIST() to riscv_cpu_options[] Daniel Henrique Barboza
2023-09-04 1:48 ` Alistair Francis
2023-09-04 7:55 ` Philippe Mathieu-Daudé
2023-09-01 19:46 ` [PATCH v9 05/20] target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[] Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 06/20] target/riscv/cpu.c: split vendor " Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 07/20] target/riscv/cpu.c: add riscv_cpu_add_qdev_prop_array() Daniel Henrique Barboza
2023-09-04 1:51 ` Alistair Francis
2023-09-04 7:59 ` Philippe Mathieu-Daudé
2023-09-01 19:46 ` [PATCH v9 08/20] target/riscv/cpu.c: add riscv_cpu_add_kvm_unavail_prop_array() Daniel Henrique Barboza
2023-09-04 2:15 ` Alistair Francis
2023-09-01 19:46 ` [PATCH v9 09/20] target/riscv/cpu.c: limit cfg->vext_spec log message Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 10/20] target/riscv: add 'max' CPU type Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 11/20] avocado, risc-v: add tuxboot tests for 'max' CPU Daniel Henrique Barboza
2023-09-04 8:22 ` Philippe Mathieu-Daudé
2023-09-07 3:47 ` Alistair Francis
2023-09-01 19:46 ` [PATCH v9 12/20] target/riscv: deprecate the 'any' CPU type Daniel Henrique Barboza
2023-09-04 8:23 ` Philippe Mathieu-Daudé
2023-09-01 19:46 ` [PATCH v9 13/20] target/riscv/cpu.c: use offset in isa_ext_is_enabled/update_enabled Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 14/20] target/riscv: make CPUCFG() macro public Daniel Henrique Barboza
2023-09-04 8:04 ` Philippe Mathieu-Daudé
2023-09-01 19:46 ` [PATCH v9 15/20] target/riscv/cpu.c: introduce cpu_cfg_ext_auto_update() Daniel Henrique Barboza
2023-09-04 9:16 ` Andrew Jones
2023-09-07 4:06 ` Alistair Francis [this message]
2023-09-01 19:46 ` [PATCH v9 16/20] target/riscv/cpu.c: use cpu_cfg_ext_auto_update() during realize() Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 17/20] target/riscv/cpu.c: introduce RISCVCPUMultiExtConfig Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 18/20] target/riscv: use isa_ext_update_enabled() in init_max_cpu_extensions() Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 19/20] target/riscv/cpu.c: honor user choice in cpu_cfg_ext_auto_update() Daniel Henrique Barboza
2023-09-01 19:46 ` [PATCH v9 20/20] target/riscv/cpu.c: consider user option with RVG Daniel Henrique Barboza
2023-09-04 9:18 ` Andrew Jones
2023-09-07 4:13 ` [PATCH v9 00/20] riscv: 'max' CPU, detect user choice in TCG Alistair Francis
2023-09-11 2:34 ` Alistair Francis
2023-09-11 9:10 ` Daniel Henrique Barboza
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAKmqyKMqeHimLKt00RQEtZXi36XL7YLQ5dfNd-ObQZRDUS78Sg@mail.gmail.com \
--to=alistair23@gmail.com \
--cc=ajones@ventanamicro.com \
--cc=alistair.francis@wdc.com \
--cc=bmeng@tinylab.org \
--cc=dbarboza@ventanamicro.com \
--cc=liweiwei@iscas.ac.cn \
--cc=palmer@rivosinc.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).